188 	struct stm32_pll_dt_cfg *pll;  member
1097 				   struct stm32_pll_dt_cfg *pll)  in clk_stm32_parse_pll_fdt()  argument
1111 	if (fdt_read_uint32_array(fdt, subnode_pll, "cfg", pll->cfg, PLLCFG_NB))  in clk_stm32_parse_pll_fdt()
1114 	err = fdt_read_uint32_array(fdt, subnode_pll, "csg", pll->csg,  in clk_stm32_parse_pll_fdt()
1117 	pll->csg_enabled = (err == 0);  in clk_stm32_parse_pll_fdt()
1125 	pll->enabled = true;  in clk_stm32_parse_pll_fdt()
1127 	pll->frac = fdt_read_uint32_default(fdt, subnode_pll, "frac", 0);  in clk_stm32_parse_pll_fdt()
1129 	if (fdt_read_uint32(fdt, subnode_pll, "src", &pll->src))  in clk_stm32_parse_pll_fdt()
1143 		struct stm32_pll_dt_cfg *pll = pdata->pll + i;  in stm32_clk_parse_fdt_all_pll()  local
1157 		if (clk_stm32_parse_pll_fdt(fdt, subnode, pll))  in stm32_clk_parse_fdt_all_pll()
1408 					const struct stm32_clk_pll *pll,  in clk_stm32_pll_config_output()  argument
1413 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_config_output()
1476 				     const struct stm32_clk_pll *pll,  in clk_stm32_pll_config_csg()  argument
1479 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_config_csg()
1511 	return &pdata->pll[pll_idx];  in clk_stm32_pll_get_pdata()
1574 	const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx);  in clk_stm32_pll_init()  local
1575 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_init()
1578 	if (stm32_gate_rdy_disable(pll->gate_id))  in clk_stm32_pll_init()
1584 	clk_stm32_pll_config_output(priv, pll, pll_conf->src,  in clk_stm32_pll_init()
1588 		clk_stm32_pll_config_csg(priv, pll, pll_conf->csg);  in clk_stm32_pll_init()
1592 	if (stm32_gate_rdy_enable(pll->gate_id))  in clk_stm32_pll_init()
3438 	.pll		= mp21_pll,