| #
d8bfc12a |
| 25-Apr-2025 |
Thomas Bourgoin <thomas.bourgoin@foss.st.com> |
plat: stm32mp2: sysconf: fix CA35SS register names
Align register names with the reference manuel for Arm Cortex-A35 (CA35SS)
- CA35SS SYSCFG registers (with 0x2000 offset)
- CA35SS Standardized sta
plat: stm32mp2: sysconf: fix CA35SS register names
Align register names with the reference manuel for Arm Cortex-A35 (CA35SS)
- CA35SS SYSCFG registers (with 0x2000 offset)
- CA35SS Standardized status and control (SSC) registers
This path removes the confusion between SSC and subsystem (SS).
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Co-developed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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|
| #
1e45c633 |
| 13-May-2025 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
clk: stm32mp21: introduce STM32MP21 clock driver
As the STM32MP25 clock driver, this driver is based on the
clk-stm32-core API to manage STM32 gates, dividers, and multiplexer.
Signed-off-by: Yann
clk: stm32mp21: introduce STM32MP21 clock driver
As the STM32MP25 clock driver, this driver is based on the
clk-stm32-core API to manage STM32 gates, dividers, and multiplexer.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
show more ...
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