133 	struct stm32_pll_dt_cfg *pll;  member
1116 				   struct stm32_pll_dt_cfg *pll)  in clk_stm32_parse_pll_fdt()  argument
1130 	if (fdt_read_uint32_array(fdt, subnode_pll, "cfg", pll->cfg, PLLCFG_NB))  in clk_stm32_parse_pll_fdt()
1133 	err = fdt_read_uint32_array(fdt, subnode_pll, "csg", pll->csg,  in clk_stm32_parse_pll_fdt()
1136 	pll->csg_enabled = (err == 0);  in clk_stm32_parse_pll_fdt()
1144 	pll->enabled = true;  in clk_stm32_parse_pll_fdt()
1146 	pll->frac = fdt_read_uint32_default(fdt, subnode_pll, "frac", 0);  in clk_stm32_parse_pll_fdt()
1148 	if (fdt_read_uint32(fdt, subnode_pll, "src", &pll->src))  in clk_stm32_parse_pll_fdt()
1162 		struct stm32_pll_dt_cfg *pll = pdata->pll + i;  in stm32_clk_parse_fdt_all_pll()  local
1172 		if (clk_stm32_parse_pll_fdt(fdt, subnode, pll))  in stm32_clk_parse_fdt_all_pll()
1426 					const struct stm32_clk_pll *pll,  in clk_stm32_pll_config_output()  argument
1431 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_config_output()
1494 				     const struct stm32_clk_pll *pll,  in clk_stm32_pll_config_csg()  argument
1497 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_config_csg()
1529 	return &pdata->pll[pll_idx];  in clk_stm32_pll_get_pdata()
1578 	const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx);  in clk_stm32_pll_init()  local
1579 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_init()
1582 	if (stm32_gate_rdy_disable(pll->gate_id))  in clk_stm32_pll_init()
1588 	clk_stm32_pll_config_output(priv, pll, pll_conf->src,  in clk_stm32_pll_init()
1592 		clk_stm32_pll_config_csg(priv, pll, pll_conf->csg);  in clk_stm32_pll_init()
1596 	if (stm32_gate_rdy_enable(pll->gate_id))  in clk_stm32_pll_init()
3534 	.pll		= mp25_pll,