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Searched refs:refdiv (Results 1 – 25 of 49) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/misc/rk628/
H A Drk628_cru.c63 u32 postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass; in rk628_cru_clk_get_rate_pll() local
94 refdiv = (con1 & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rk628_cru_clk_get_rate_pll()
101 do_div(foutvco, refdiv); in rk628_cru_clk_get_rate_pll()
106 do_div(frac_rate, refdiv); in rk628_cru_clk_get_rate_pll()
123 u8 dsmpd = 1, postdiv1 = 0, postdiv2 = 0, refdiv = 0; in rk628_cru_clk_set_rate_pll() local
186 for (refdiv = min_refdiv; refdiv <= max_refdiv; refdiv++) { in rk628_cru_clk_set_rate_pll()
189 if (fin % refdiv) in rk628_cru_clk_set_rate_pll()
192 tmp = (u64)fout * refdiv; in rk628_cru_clk_set_rate_pll()
199 do_div(tmp, refdiv); in rk628_cru_clk_set_rate_pll()
206 tmp = (u64)frac_rate * refdiv; in rk628_cru_clk_set_rate_pll()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/mmp/
H A Dclk-pll.c49 u32 fbdiv, refdiv, postdiv; in mmp_clk_pll_recalc_rate() local
60 refdiv = (val >> (pll->shift + 9)) & 0x1f; in mmp_clk_pll_recalc_rate()
63 refdiv = 1; in mmp_clk_pll_recalc_rate()
75 do_div(rate, refdiv); in mmp_clk_pll_recalc_rate()
79 if (refdiv == 3) { in mmp_clk_pll_recalc_rate()
81 } else if (refdiv == 4) { in mmp_clk_pll_recalc_rate()
84 pr_err("bad refdiv: %d (0x%08x)\n", refdiv, val); in mmp_clk_pll_recalc_rate()
89 do_div(rate, refdiv + 2); in mmp_clk_pll_recalc_rate()
/OK3568_Linux_fs/kernel/drivers/media/i2c/rk628/
H A Drk628_cru.c64 u32 postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass; in rk628_cru_clk_get_rate_pll() local
95 refdiv = (con1 & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rk628_cru_clk_get_rate_pll()
102 do_div(foutvco, refdiv); in rk628_cru_clk_get_rate_pll()
107 do_div(frac_rate, refdiv); in rk628_cru_clk_get_rate_pll()
124 u8 dsmpd = 1, postdiv1 = 0, postdiv2 = 0, refdiv = 0; in rk628_cru_clk_set_rate_pll() local
192 for (refdiv = min_refdiv; refdiv <= max_refdiv; refdiv++) { in rk628_cru_clk_set_rate_pll()
195 if (fin % refdiv) in rk628_cru_clk_set_rate_pll()
198 tmp = (u64)fout * refdiv; in rk628_cru_clk_set_rate_pll()
205 do_div(tmp, refdiv); in rk628_cru_clk_set_rate_pll()
212 tmp = (u64)frac_rate * refdiv; in rk628_cru_clk_set_rate_pll()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/
H A Dclk-regmap-pll.c69 unsigned int postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass; in clk_regmap_pll_recalc_rate() local
82 refdiv = (con1 & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in clk_regmap_pll_recalc_rate()
89 do_div(foutvco, refdiv); in clk_regmap_pll_recalc_rate()
94 do_div(frac_rate, refdiv); in clk_regmap_pll_recalc_rate()
106 u8 *refdiv, u16 *fbdiv, in clk_pll_round_rate() argument
214 if (refdiv) in clk_pll_round_rate()
215 *refdiv = _refdiv; in clk_pll_round_rate()
253 u8 refdiv, postdiv1, postdiv2, dsmpd, bypass; in clk_regmap_pll_set_rate() local
258 rate = clk_pll_round_rate(prate, drate, &refdiv, &fbdiv, &postdiv1, in clk_regmap_pll_set_rate()
275 PLL_POSTDIV2(postdiv2) | PLL_REFDIV(refdiv)); in clk_regmap_pll_set_rate()
[all …]
/OK3568_Linux_fs/u-boot/arch/mips/mach-ath79/ar934x/
H A Dclk.c32 u8 refdiv; member
145 pll_refdiv = pll_cfg->refdiv; in ar934x_pll_init()
154 pll_refdiv = pll_cfg->refdiv; in ar934x_pll_init()
233 const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & in ar934x_cpupll_to_hz() local
241 return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); in ar934x_cpupll_to_hz()
248 const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & in ar934x_ddrpll_to_hz() local
256 return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); in ar934x_ddrpll_to_hz()
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_pll.c132 rate_table->refdiv = fin_hz / clk_gcd; in rockchip_pll_clk_set_by_auto()
140 rate_table->refdiv, in rockchip_pll_clk_set_by_auto()
149 rate_table->refdiv = fin_hz / MHZ / clk_gcd; in rockchip_pll_clk_set_by_auto()
152 rate_table->refdiv, rate_table->fbdiv); in rockchip_pll_clk_set_by_auto()
158 fin_64 = fin_64 / rate_table->refdiv; in rockchip_pll_clk_set_by_auto()
262 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); in rk3036_pll_set_rate()
289 rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT)); in rk3036_pll_set_rate()
330 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; in rk3036_pll_get_rate() local
357 refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >> in rk3036_pll_get_rate()
364 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rk3036_pll_get_rate()
[all …]
H A Dclk_rk3399.c36 u32 refdiv; member
49 .refdiv = _refdiv,\
344 u32 refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
358 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
359 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
369 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
374 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
398 (div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
447 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_para_config() local
480 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { in pll_para_config()
[all …]
H A Dclk_rk3036.c50 .refdiv = _refdiv,\
69 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
74 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
90 div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
204 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
234 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
235 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
H A Dclk_rv1108.c32 .refdiv = _refdiv,\
72 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
76 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
97 div->refdiv << REFDIV_SHIFT)); in rkclk_set_pll()
99 (div->refdiv << REFDIV_SHIFT)); in rkclk_set_pll()
120 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
134 refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK; in rkclk_pll_get_rate()
135 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
H A Dclk_px30.c38 .refdiv = _refdiv, \
110 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_clk_set_by_auto() local
143 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { in pll_clk_set_by_auto()
144 fref_khz = ref_khz / refdiv; in pll_clk_set_by_auto()
159 rate->refdiv = refdiv; in pll_clk_set_by_auto()
228 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; in rkclk_set_pll()
232 pll, rate->fbdiv, rate->refdiv, rate->postdiv1, in rkclk_set_pll()
254 rate->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
272 u32 refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
289 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-pll.c222 rate_table->refdiv = fin_hz / clk_gcd; in rockchip_pll_clk_set_by_auto()
228 fin_hz, fout_hz, clk_gcd, rate_table->refdiv, in rockchip_pll_clk_set_by_auto()
239 rate_table->refdiv = fin_hz / MHZ / clk_gcd; in rockchip_pll_clk_set_by_auto()
242 rate_table->refdiv, rate_table->fbdiv); in rockchip_pll_clk_set_by_auto()
248 do_div(fin_64, (u64)rate_table->refdiv); in rockchip_pll_clk_set_by_auto()
490 unsigned int fbdiv, postdiv1, refdiv, postdiv2; in rockchip_rk3036_pll_con_to_rate() local
497 refdiv = ((con1 >> RK3036_PLLCON1_REFDIV_SHIFT) & in rockchip_rk3036_pll_con_to_rate()
503 do_div(rate64, refdiv); in rockchip_rk3036_pll_con_to_rate()
522 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) in rockchip_rk3036_pll_get_params()
547 do_div(rate64, cur.refdiv); in rockchip_rk3036_pll_recalc_rate()
[all …]
/OK3568_Linux_fs/kernel/arch/mips/ath25/
H A Dar2315.c207 unsigned int pllc_out, refdiv, fdiv, divby2; in ar2315_sys_clk() local
211 refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV); in ar2315_sys_clk()
212 refdiv = clockctl1_predivide_table[refdiv]; in ar2315_sys_clk()
215 pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv; in ar2315_sys_clk()
/OK3568_Linux_fs/kernel/drivers/clk/pistachio/
H A Dclk-pll.c206 if (!params || !params->refdiv) in pll_gf40lp_frac_set_rate()
212 vco = div64_u64(vco, params->refdiv << 24); in pll_gf40lp_frac_set_rate()
218 val = div64_u64(params->fref, params->refdiv); in pll_gf40lp_frac_set_rate()
229 val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) | in pll_gf40lp_frac_set_rate()
363 if (!params || !params->refdiv) in pll_gf40lp_laint_set_rate()
366 vco = div_u64(params->fref * params->fbdiv, params->refdiv); in pll_gf40lp_laint_set_rate()
371 val = div_u64(params->fref, params->refdiv); in pll_gf40lp_laint_set_rate()
397 val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) | in pll_gf40lp_laint_set_rate()
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath10k/
H A Dhw.c487 .refdiv = 0,
495 .refdiv = 0,
503 .refdiv = 0,
511 .refdiv = 0,
519 .refdiv = 0,
527 .refdiv = 0,
535 .refdiv = 0,
543 .refdiv = 0,
820 reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) | in ath10k_hw_qca6174_enable_pll_clock()
/OK3568_Linux_fs/kernel/drivers/clk/berlin/
H A Dberlin2-avpll.c159 u32 reg, refdiv, fbdiv; in berlin2_avpll_vco_recalc_rate() local
164 refdiv = (reg & VCO_REFDIV_MASK) >> VCO_REFDIV_SHIFT; in berlin2_avpll_vco_recalc_rate()
165 refdiv = vco_refdiv[refdiv]; in berlin2_avpll_vco_recalc_rate()
168 do_div(freq, refdiv); in berlin2_avpll_vco_recalc_rate()
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Dcx24113.c85 u8 refdiv; member
281 static u8 cx24113_set_ref_div(struct cx24113_state *state, u8 refdiv) in cx24113_set_ref_div() argument
284 refdiv = 2; in cx24113_set_ref_div()
285 return state->refdiv = refdiv; in cx24113_set_ref_div()
396 cx24113_set_nfr(state, n, f, state->refdiv); in cx24113_set_frequency()
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Darizona.c2098 int refdiv; member
2155 int refdiv, div; in arizona_calc_fratio() local
2159 cfg->refdiv = 0; in arizona_calc_fratio()
2163 cfg->refdiv++; in arizona_calc_fratio()
2195 refdiv = cfg->refdiv; in arizona_calc_fratio()
2198 init_ratio, Fref, refdiv); in arizona_calc_fratio()
2206 cfg->refdiv = refdiv; in arizona_calc_fratio()
2210 Fref, refdiv, div, ratio); in arizona_calc_fratio()
2232 cfg->refdiv = refdiv; in arizona_calc_fratio()
2236 Fref, refdiv, div, ratio); in arizona_calc_fratio()
[all …]
H A Dmadera.c3509 int refdiv, div; in madera_calc_fratio() local
3513 cfg->refdiv = 0; in madera_calc_fratio()
3517 cfg->refdiv++; in madera_calc_fratio()
3558 refdiv = cfg->refdiv; in madera_calc_fratio()
3567 cfg->refdiv = refdiv; in madera_calc_fratio()
3583 cfg->refdiv = refdiv; in madera_calc_fratio()
3591 refdiv++; in madera_calc_fratio()
3639 fref = fref / (1 << cfg->refdiv); in madera_calc_fll()
3708 cfg->fratio, ratio, cfg->refdiv, 1 << cfg->refdiv); in madera_calc_fll()
3741 cfg->refdiv << MADERA_FLL1_REFCLK_DIV_SHIFT | in madera_write_fll()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/socfpga/
H A Dclk-pll-s10.c60 unsigned long refdiv; in clk_pll_recalc_rate() local
66 refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT; in clk_pll_recalc_rate()
69 do_div(vco_freq, refdiv); in clk_pll_recalc_rate()
/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3308.c94 pll_priv->refdiv << REFDIV_SHIFT); in pll_set()
132 rk3308_pll_div.refdiv = 2; in rkdclk_init()
142 rk3308_pll_div.refdiv = 2; in rkdclk_init()
150 rk3308_pll_div.refdiv = 2; in rkdclk_init()
186 rk3308_pll_div.refdiv = 1; in rkdclk_init()
194 rk3308_pll_div.refdiv = 6; in rkdclk_init()
263 rk3308_pll_div.refdiv = 2; in rkdclk_init()
326 rk3308_pll_div.refdiv = 6; in rkdclk_init()
H A Dsdram_rk3328.c79 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
83 refdiv = 1; in rkclk_set_dpll()
103 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
107 writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv), in rkclk_set_dpll()
H A Dsdram_px30.c78 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
82 refdiv = 1; in rkclk_set_dpll()
102 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
107 writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv), in rkclk_set_dpll()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h73 .refdiv = _refdiv, \
97 unsigned int refdiv; member
/OK3568_Linux_fs/u-boot/arch/m68k/cpu/mcf532x/
H A Dspeed.c69 u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); in get_sys_clock() local
72 return (((FREF * pfdr) / refdiv) / busdiv); in get_sys_clock()
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-axm5516.c52 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
58 refdiv = ((control >> 16) & 0x1f) + 1; in axxia_pllclk_recalc()
59 rate = (parent_rate / (refdiv * postdiv)) * fbdiv; in axxia_pllclk_recalc()

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