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Searched refs:postdiv (Results 1 – 25 of 32) sorted by relevance

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/OK3568_Linux_fs/kernel/arch/mips/ath79/
H A Dclock.c238 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_clocks_init() local
309 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & in ar934x_clocks_init()
315 cpu_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
317 cpu_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
319 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & in ar934x_clocks_init()
325 ddr_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
327 ddr_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
329 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & in ar934x_clocks_init()
335 ahb_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
337 ahb_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-pll.c63 u32 pcw, int postdiv) in __mtk_pll_recalc_rate() argument
86 return ((unsigned long)vco + postdiv - 1) / postdiv; in __mtk_pll_recalc_rate()
116 int postdiv) in mtk_pll_set_rate_regs() argument
126 val |= (ffs(postdiv) - 1) << pll->data->pd_shift; in mtk_pll_set_rate_regs()
159 static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, in mtk_pll_calc_values() argument
179 *postdiv = 1 << val; in mtk_pll_calc_values()
182 *postdiv = 1 << val; in mtk_pll_calc_values()
183 if ((u64)freq * *postdiv >= fmin) in mtk_pll_calc_values()
201 u32 postdiv; in mtk_pll_set_rate() local
203 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_pll_set_rate()
[all …]
/OK3568_Linux_fs/kernel/arch/mips/ar7/
H A Dclock.c72 u32 postdiv; member
99 int *postdiv, int *mul) in approximate() argument
110 *postdiv = k; in approximate()
115 static void calculate(int base, int target, int *prediv, int *postdiv, in calculate() argument
124 *postdiv = tmp_base / tmp_gcd; in calculate()
127 if ((*postdiv > 0) & (*postdiv <= 32)) in calculate()
131 if (base / *prediv * *mul / *postdiv != target) { in calculate()
132 approximate(base, target, prediv, postdiv, mul); in calculate()
133 tmp_freq = base / *prediv * *mul / *postdiv; in calculate()
140 *prediv, *postdiv, *mul); in calculate()
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/OK3568_Linux_fs/kernel/drivers/clk/mmp/
H A Dclk-audio.c119 unsigned int postdiv; in audio_pll_recalc_rate() local
138 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_recalc_rate()
144 val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo); in audio_pll_recalc_rate()
152 val |= SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(postdivs[postdiv].pattern); in audio_pll_recalc_rate()
157 freq /= postdivs[postdiv].divisor; in audio_pll_recalc_rate()
169 unsigned int postdiv; in audio_pll_round_rate() local
175 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_round_rate()
178 freq /= postdivs[postdiv].divisor; in audio_pll_round_rate()
197 unsigned int postdiv; in audio_pll_set_rate() local
204 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_set_rate()
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H A Dclk-pll.c49 u32 fbdiv, refdiv, postdiv; in mmp_clk_pll_recalc_rate() local
71 postdiv = (val >> pll->postdiv_shift) & 0x7; in mmp_clk_pll_recalc_rate()
76 do_div(rate, postdivs[postdiv]); in mmp_clk_pll_recalc_rate()
/OK3568_Linux_fs/kernel/drivers/clk/keystone/
H A Dpll.c60 u32 postdiv; member
81 u32 mult = 0, prediv, postdiv, val; in clk_pllclk_recalc() local
100 postdiv = ((val & pll_data->clkod_mask) >> in clk_pllclk_recalc()
103 postdiv = readl(pll_data->pllod); in clk_pllclk_recalc()
104 postdiv = ((postdiv & pll_data->clkod_mask) >> in clk_pllclk_recalc()
107 postdiv = pll_data->postdiv; in clk_pllclk_recalc()
111 rate /= postdiv; in clk_pllclk_recalc()
172 if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) { in _of_pll_clk_init()
/OK3568_Linux_fs/kernel/arch/c6x/platforms/
H A Dpll.c267 u32 ctrl, mult = 0, prediv = 0, postdiv = 0; in clk_pllclk_recalc() local
295 postdiv = pll_read(pll, PLLPOST); in clk_pllclk_recalc()
296 if (postdiv & PLLDIV_EN) in clk_pllclk_recalc()
297 postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1; in clk_pllclk_recalc()
299 postdiv = 1; in clk_pllclk_recalc()
307 if (postdiv) in clk_pllclk_recalc()
308 rate /= postdiv; in clk_pllclk_recalc()
313 prediv, mult, postdiv, rate / 1000000); in clk_pllclk_recalc()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dsi/pll/
H A Ddsi_pll_14nm.c680 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); in dsi_pll_14nm_postdiv_recalc_rate() local
681 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_recalc_rate()
683 u8 shift = postdiv->shift; in dsi_pll_14nm_postdiv_recalc_rate()
684 u8 width = postdiv->width; in dsi_pll_14nm_postdiv_recalc_rate()
693 postdiv->flags, width); in dsi_pll_14nm_postdiv_recalc_rate()
700 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); in dsi_pll_14nm_postdiv_round_rate() local
701 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_round_rate()
706 postdiv->width, in dsi_pll_14nm_postdiv_round_rate()
707 postdiv->flags); in dsi_pll_14nm_postdiv_round_rate()
713 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); in dsi_pll_14nm_postdiv_set_rate() local
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/rk628/
H A Drk628_cru.c123 u8 min_refdiv, max_refdiv, postdiv, div1, div2; in rk628_cru_clk_set_rate_pll() local
166 for (postdiv = div1; postdiv <= div2; postdiv++) { in rk628_cru_clk_set_rate_pll()
169 if (postdiv % postdiv2) in rk628_cru_clk_set_rate_pll()
172 postdiv1 = postdiv / postdiv2; in rk628_cru_clk_set_rate_pll()
183 if (postdiv > div2) in rk628_cru_clk_set_rate_pll()
/OK3568_Linux_fs/kernel/arch/arm/mach-davinci/
H A Dda850.c361 unsigned int postdiv; member
370 .postdiv = 1,
379 .postdiv = 1,
388 .postdiv = 1,
397 .postdiv = 2,
406 .postdiv = 3,
415 .postdiv = 5,
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dkeystone-pll.txt20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
21 for postdiv
30 fixed-postdiv = <2>;
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/
H A Dclk-regmap-pll.c110 u8 min_refdiv, max_refdiv, postdiv; in clk_pll_round_rate() local
140 postdiv = DIV_ROUND_UP_ULL(MIN_FVCO_RATE, fout); in clk_pll_round_rate()
143 if (postdiv % _postdiv2) in clk_pll_round_rate()
146 _postdiv1 = postdiv / _postdiv2; in clk_pll_round_rate()
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-composite-8m.c52 int *prediv, int *postdiv) in imx8m_clk_composite_compute_dividers() argument
59 *postdiv = 1; in imx8m_clk_composite_compute_dividers()
67 *postdiv = div2; in imx8m_clk_composite_compute_dividers()
/OK3568_Linux_fs/kernel/drivers/misc/rk628/
H A Drk628_cru.c122 u8 min_refdiv, max_refdiv, postdiv; in rk628_cru_clk_set_rate_pll() local
165 postdiv = MIN_FVCO_RATE / fout + 1; in rk628_cru_clk_set_rate_pll()
168 if (postdiv % postdiv2) in rk628_cru_clk_set_rate_pll()
171 postdiv1 = postdiv / postdiv2; in rk628_cru_clk_set_rate_pll()
/OK3568_Linux_fs/kernel/drivers/video/fbdev/
H A Dgxt4500.c238 int m, n, pdiv1, pdiv2, postdiv; in calc_pll() local
248 postdiv = pdiv1 * pdiv2; in calc_pll()
249 pll_period = DIV_ROUND_UP(period_ps, postdiv); in calc_pll()
257 n = intf * postdiv / period_ps; in calc_pll()
260 t = par->refclk_ps * m * postdiv / n; in calc_pll()
/OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/
H A Dda850_lowlevel.c95 &reg->postdiv); in da850_pll_init()
98 &reg->postdiv); in da850_pll_init()
H A Ddm365_lowlevel.c72 writel(PLL_POSTDEN, &dv_pll0_regs->postdiv); in dm365_pll1_init()
142 writel(PLL_POSTDEN, &dv_pll1_regs->postdiv); in dm365_pll2_init()
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-axm5516.c52 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
56 postdiv = ((control >> 0) & 0xf) + 1; in axxia_pllclk_recalc()
59 rate = (parent_rate / (refdiv * postdiv)) * fbdiv; in axxia_pllclk_recalc()
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Drockchip-inno-hdmi-phy.c195 u8 postdiv; member
596 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3228_power_on()
608 v = POST_PLL_POST_DIV(cfg->postdiv / 2 - 1); in inno_hdmi_phy_rk3228_power_on()
733 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3328_power_on()
738 val = (cfg->postdiv / 2) - 1; in inno_hdmi_phy_rk3328_power_on()
927 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3528_power_on()
931 val = (cfg->postdiv / 2) - 1; in inno_hdmi_phy_rk3528_power_on()
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-inno-hdmi-phy.c210 u8 postdiv; member
737 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3228_power_on()
749 v = POST_PLL_POST_DIV(cfg->postdiv / 2 - 1); in inno_hdmi_phy_rk3228_power_on()
909 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3328_power_on()
914 val = (cfg->postdiv / 2) - 1; in inno_hdmi_phy_rk3328_power_on()
1133 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3528_power_on()
1137 val = (cfg->postdiv / 2) - 1; in inno_hdmi_phy_rk3528_power_on()
H A Dphy-rockchip-inno-hdmi.c270 u8 postdiv; member
917 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3228_power_on()
921 int div = cfg->postdiv / 2 - 1; in inno_hdmi_phy_rk3228_power_on()
1023 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3328_power_on()
1028 v = (cfg->postdiv / 2) - 1; in inno_hdmi_phy_rk3328_power_on()
/OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h25 unsigned int postdiv; /* 0x128 */ member
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c684 table->SclkFcwRangeTable[i].postdiv = in vegam_get_sclk_range_table()
703 (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; in vegam_get_sclk_range_table()
705 (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; in vegam_get_sclk_range_table()
708 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; in vegam_get_sclk_range_table()
761 ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
763 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in vegam_calculate_sclk_params()
771 ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
780 ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
782 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in vegam_calculate_sclk_params()
H A Dpolaris10_smumgr.c812 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv; in polaris10_get_sclk_range_table()
826 …le[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
827 …le[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
830 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
882 …_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
883 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in polaris10_calculate_sclk_params()
890 …nt16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
897 …int16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
898 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in polaris10_calculate_sclk_params()
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_pll.c524 u64 rate, postdiv; in rk3588_pll_get_rate() local
555 postdiv = p * 65536; in rk3588_pll_get_rate()
556 do_div(frac_rate64, postdiv); in rk3588_pll_get_rate()

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