1*4882a593SmuzhiyunStatus: Unstable - ABI compatibility may be broken in the future 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunBinding for keystone PLLs. The main PLL IP typically has a multiplier, 4*4882a593Smuzhiyuna divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL 5*4882a593Smuzhiyunand PAPLL are controlled by the memory mapped register where as the Main 6*4882a593SmuzhiyunPLL is controlled by a PLL controller registers along with memory mapped 7*4882a593Smuzhiyunregisters. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThis binding uses the common clock binding[1]. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunRequired properties: 14*4882a593Smuzhiyun- #clock-cells : from common clock binding; shall be set to 0. 15*4882a593Smuzhiyun- compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock" 16*4882a593Smuzhiyun- clocks : parent clock phandle 17*4882a593Smuzhiyun- reg - pll control0 and pll multipler registers 18*4882a593Smuzhiyun- reg-names : control, multiplier and post-divider. The multiplier and 19*4882a593Smuzhiyun post-divider registers are applicable only for main pll clock 20*4882a593Smuzhiyun- fixed-postdiv : fixed post divider value. If absent, use clkod register bits 21*4882a593Smuzhiyun for postdiv 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun mainpllclk: mainpllclk@2310110 { 25*4882a593Smuzhiyun #clock-cells = <0>; 26*4882a593Smuzhiyun compatible = "ti,keystone,main-pll-clock"; 27*4882a593Smuzhiyun clocks = <&refclksys>; 28*4882a593Smuzhiyun reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; 29*4882a593Smuzhiyun reg-names = "control", "multiplier", "post-divider"; 30*4882a593Smuzhiyun fixed-postdiv = <2>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun papllclk: papllclk@2620358 { 34*4882a593Smuzhiyun #clock-cells = <0>; 35*4882a593Smuzhiyun compatible = "ti,keystone,pll-clock"; 36*4882a593Smuzhiyun clocks = <&refclkpass>; 37*4882a593Smuzhiyun clock-output-names = "pa-pll-clk"; 38*4882a593Smuzhiyun reg = <0x02620358 4>; 39*4882a593Smuzhiyun reg-names = "control"; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunRequired properties: 43*4882a593Smuzhiyun- #clock-cells : from common clock binding; shall be set to 0. 44*4882a593Smuzhiyun- compatible : shall be "ti,keystone,pll-mux-clock" 45*4882a593Smuzhiyun- clocks : link phandles of parent clocks 46*4882a593Smuzhiyun- reg - pll mux register 47*4882a593Smuzhiyun- bit-shift : number of bits to shift the bit-mask 48*4882a593Smuzhiyun- bit-mask : arbitrary bitmask for programming the mux 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunOptional properties: 51*4882a593Smuzhiyun- clock-output-names : From common clock binding. 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunExample: 54*4882a593Smuzhiyun mainmuxclk: mainmuxclk@2310108 { 55*4882a593Smuzhiyun #clock-cells = <0>; 56*4882a593Smuzhiyun compatible = "ti,keystone,pll-mux-clock"; 57*4882a593Smuzhiyun clocks = <&mainpllclk>, <&refclkmain>; 58*4882a593Smuzhiyun reg = <0x02310108 4>; 59*4882a593Smuzhiyun bit-shift = <23>; 60*4882a593Smuzhiyun bit-mask = <1>; 61*4882a593Smuzhiyun clock-output-names = "mainmuxclk"; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunRequired properties: 65*4882a593Smuzhiyun- #clock-cells : from common clock binding; shall be set to 0. 66*4882a593Smuzhiyun- compatible : shall be "ti,keystone,pll-divider-clock" 67*4882a593Smuzhiyun- clocks : parent clock phandle 68*4882a593Smuzhiyun- reg - pll mux register 69*4882a593Smuzhiyun- bit-shift : number of bits to shift the bit-mask 70*4882a593Smuzhiyun- bit-mask : arbitrary bitmask for programming the divider 71*4882a593Smuzhiyun 72*4882a593SmuzhiyunOptional properties: 73*4882a593Smuzhiyun- clock-output-names : From common clock binding. 74*4882a593Smuzhiyun 75*4882a593SmuzhiyunExample: 76*4882a593Smuzhiyun gemtraceclk: gemtraceclk@2310120 { 77*4882a593Smuzhiyun #clock-cells = <0>; 78*4882a593Smuzhiyun compatible = "ti,keystone,pll-divider-clock"; 79*4882a593Smuzhiyun clocks = <&mainmuxclk>; 80*4882a593Smuzhiyun reg = <0x02310120 4>; 81*4882a593Smuzhiyun bit-shift = <0>; 82*4882a593Smuzhiyun bit-mask = <8>; 83*4882a593Smuzhiyun clock-output-names = "gemtraceclk"; 84*4882a593Smuzhiyun }; 85