1 /*
2 * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/delay.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/iopoll.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/nvmem-consumer.h>
25 #include <linux/of.h>
26 #include <linux/phy/phy.h>
27 #include <linux/platform_device.h>
28 #include <linux/regmap.h>
29 #include <linux/rockchip/cpu.h>
30 #include <linux/slab.h>
31
32 #define INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT 1000
33
34 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
35
36 /* REG: 0x00 */
37 #define PRE_PLL_REFCLK_SEL_MASK BIT(0)
38 #define PRE_PLL_REFCLK_SEL_PCLK BIT(0)
39 #define PRE_PLL_REFCLK_SEL_OSCCLK 0
40 /* REG: 0x01 */
41 #define BYPASS_RXSENSE_EN_MASK BIT(2)
42 #define BYPASS_RXSENSE_EN BIT(2)
43 #define BYPASS_PWRON_EN_MASK BIT(1)
44 #define BYPASS_PWRON_EN BIT(1)
45 #define BYPASS_PLLPD_EN_MASK BIT(0)
46 #define BYPASS_PLLPD_EN BIT(0)
47 /* REG: 0x02 */
48 #define BYPASS_PDATA_EN_MASK BIT(4)
49 #define BYPASS_PDATA_EN BIT(4)
50 #define PDATAEN_MASK BIT(0)
51 #define PDATAEN_DISABLE BIT(0)
52 #define PDATAEN_ENABLE 0
53 /* REG: 0x03 */
54 #define BYPASS_AUTO_TERM_RES_CAL BIT(7)
55 #define AUDO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0)
56 /* REG: 0x04 */
57 #define AUDO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0)
58 /* REG: 0xaa */
59 #define POST_PLL_CTRL_MASK BIT(0)
60 #define POST_PLL_CTRL_MANUAL BIT(0)
61 /* REG: 0xe0 */
62 #define POST_PLL_POWER_MASK BIT(5)
63 #define POST_PLL_POWER_DOWN BIT(5)
64 #define POST_PLL_POWER_UP 0
65 #define PRE_PLL_POWER_MASK BIT(4)
66 #define PRE_PLL_POWER_DOWN BIT(4)
67 #define PRE_PLL_POWER_UP 0
68 #define RXSENSE_CLK_CH_MASK BIT(3)
69 #define RXSENSE_CLK_CH_ENABLE BIT(3)
70 #define RXSENSE_DATA_CH2_MASK BIT(2)
71 #define RXSENSE_DATA_CH2_ENABLE BIT(2)
72 #define RXSENSE_DATA_CH1_MASK BIT(1)
73 #define RXSENSE_DATA_CH1_ENABLE BIT(1)
74 #define RXSENSE_DATA_CH0_MASK BIT(0)
75 #define RXSENSE_DATA_CH0_ENABLE BIT(0)
76 /* REG: 0xe1 */
77 #define BANDGAP_MASK BIT(4)
78 #define BANDGAP_ENABLE BIT(4)
79 #define BANDGAP_DISABLE 0
80 #define TMDS_DRIVER_MASK GENMASK(3, 0)
81 #define TMDS_DRIVER_ENABLE UPDATE(0xf, 3, 0)
82 #define TMDS_DRIVER_DISABLE 0
83 /* REG: 0xe2 */
84 #define PRE_PLL_FB_DIV_8_MASK BIT(7)
85 #define PRE_PLL_FB_DIV_8_SHIFT 7
86 #define PRE_PLL_FB_DIV_8(x) UPDATE(x, 7, 7)
87 #define PCLK_VCO_DIV_5_MASK BIT(5)
88 #define PCLK_VCO_DIV_5_SHIFT 5
89 #define PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5)
90 #define PRE_PLL_PRE_DIV_MASK GENMASK(4, 0)
91 #define PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
92 /* REG: 0xe3 */
93 #define PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
94 /* REG: 0xe4 */
95 #define PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5)
96 #define PRE_PLL_PCLK_DIV_B_SHIFT 5
97 #define PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)
98 #define PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0)
99 #define PRE_PLL_PCLK_DIV_A_SHIFT 0
100 #define PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0)
101 /* REG: 0xe5 */
102 #define PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5)
103 #define PRE_PLL_PCLK_DIV_C_SHIFT 5
104 #define PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5)
105 #define PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0)
106 #define PRE_PLL_PCLK_DIV_D_SHIFT 0
107 #define PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0)
108 /* REG: 0xe6 */
109 #define PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(5, 4)
110 #define PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 5, 4)
111 #define PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(3, 2)
112 #define PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 3, 2)
113 #define PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(1, 0)
114 #define PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 1, 0)
115 /* REG: 0xe8 */
116 #define PRE_PLL_LOCK_STATUS BIT(0)
117 /* REG: 0xe9 */
118 #define POST_PLL_POST_DIV_EN_MASK GENMASK(7, 6)
119 #define POST_PLL_POST_DIV_ENABLE UPDATE(3, 7, 6)
120 #define POST_PLL_POST_DIV_DISABLE 0
121 #define POST_PLL_PRE_DIV_MASK GENMASK(4, 0)
122 #define POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
123 /* REG: 0xea */
124 #define POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
125 /* REG: 0xeb */
126 #define POST_PLL_FB_DIV_8_MASK BIT(7)
127 #define POST_PLL_FB_DIV_8(x) UPDATE(x, 7, 7)
128 #define POST_PLL_POST_DIV_MASK GENMASK(5, 4)
129 #define POST_PLL_POST_DIV(x) UPDATE(x, 5, 4)
130 #define POST_PLL_LOCK_STATUS BIT(0)
131 /* REG: 0xee */
132 #define TMDS_CH_TA_MASK GENMASK(7, 4)
133 #define TMDS_CH_TA_ENABLE UPDATE(0xf, 7, 4)
134 #define TMDS_CH_TA_DISABLE 0
135 /* REG: 0xef */
136 #define TMDS_CLK_CH_TA(x) UPDATE(x, 7, 6)
137 #define TMDS_DATA_CH2_TA(x) UPDATE(x, 5, 4)
138 #define TMDS_DATA_CH1_TA(x) UPDATE(x, 3, 2)
139 #define TMDS_DATA_CH0_TA(x) UPDATE(x, 1, 0)
140 /* REG: 0xf0 */
141 #define TMDS_DATA_CH2_PRE_EMPHASIS_MASK GENMASK(5, 4)
142 #define TMDS_DATA_CH2_PRE_EMPHASIS(x) UPDATE(x, 5, 4)
143 #define TMDS_DATA_CH1_PRE_EMPHASIS_MASK GENMASK(3, 2)
144 #define TMDS_DATA_CH1_PRE_EMPHASIS(x) UPDATE(x, 3, 2)
145 #define TMDS_DATA_CH0_PRE_EMPHASIS_MASK GENMASK(1, 0)
146 #define TMDS_DATA_CH0_PRE_EMPHASIS(x) UPDATE(x, 1, 0)
147 /* REG: 0xf1 */
148 #define TMDS_CLK_CH_OUTPUT_SWING(x) UPDATE(x, 7, 4)
149 #define TMDS_DATA_CH2_OUTPUT_SWING(x) UPDATE(x, 3, 0)
150 /* REG: 0xf2 */
151 #define TMDS_DATA_CH1_OUTPUT_SWING(x) UPDATE(x, 7, 4)
152 #define TMDS_DATA_CH0_OUTPUT_SWING(x) UPDATE(x, 3, 0)
153
154 enum inno_hdmi_phy_type {
155 INNO_HDMI_PHY_RK3228,
156 INNO_HDMI_PHY_RK3328,
157 INNO_HDMI_PHY_RK3528
158 };
159
160 struct phy_config {
161 unsigned long tmdsclock;
162 u8 regs[14];
163 };
164
165 struct inno_hdmi_phy_drv_data;
166
167 struct inno_hdmi_phy {
168 struct device *dev;
169 struct regmap *regmap;
170
171 int irq;
172
173 struct phy *phy;
174 struct clk *sysclk;
175 struct phy_config *phy_cfg;
176
177 /* platform data */
178 struct inno_hdmi_phy_drv_data *plat_data;
179
180 /* efuse flag */
181 bool efuse_flag;
182
183 /* clk provider */
184 struct clk_hw hw;
185 struct clk *pclk;
186 unsigned long pixclock;
187 unsigned long tmdsclock;
188 };
189
190 struct pre_pll_config {
191 unsigned long pixclock;
192 unsigned long tmdsclock;
193 u8 prediv;
194 u16 fbdiv;
195 u8 tmds_div_a;
196 u8 tmds_div_b;
197 u8 tmds_div_c;
198 u8 pclk_div_a;
199 u8 pclk_div_b;
200 u8 pclk_div_c;
201 u8 pclk_div_d;
202 u8 vco_div_5_en;
203 u32 fracdiv;
204 };
205
206 struct post_pll_config {
207 unsigned long tmdsclock;
208 u8 prediv;
209 u16 fbdiv;
210 u8 postdiv;
211 u8 version;
212 };
213
214 struct inno_hdmi_phy_ops {
215 void (*init)(struct inno_hdmi_phy *inno);
216 int (*power_on)(struct inno_hdmi_phy *inno,
217 const struct post_pll_config *cfg,
218 const struct phy_config *phy_cfg);
219 void (*power_off)(struct inno_hdmi_phy *inno);
220 int (*pre_pll_update)(struct inno_hdmi_phy *inno,
221 const struct pre_pll_config *cfg);
222 unsigned long (*recalc_rate)(struct inno_hdmi_phy *inno,
223 unsigned long parent_rate);
224 };
225
226 struct inno_hdmi_phy_drv_data {
227 enum inno_hdmi_phy_type dev_type;
228 const struct inno_hdmi_phy_ops *ops;
229 const struct phy_config *phy_cfg_table;
230 };
231
232 /*
233 * If only using integer freq div can't get frequency we want, frac
234 * freq div is needed. For example, pclk 88.75 Mhz and tmdsclk
235 * 110.9375 Mhz must use frac div 0xF00000. The actual frequency is different
236 * from the target frequency. Such as the tmds clock 110.9375 Mhz,
237 * the actual tmds clock we get is 110.93719 Mhz. It is important
238 * to note that RK322X platforms do not support frac div.
239 */
240 static const struct pre_pll_config pre_pll_cfg_table[] = {
241 { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
242 { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
243 { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
244 { 40000000, 50000000, 1, 100, 2, 2, 2, 1, 0, 0, 15, 0, 0},
245 { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B},
246 { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0},
247 { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B},
248 { 59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0},
249 { 65000000, 65000000, 1, 130, 2, 2, 2, 1, 0, 0, 12, 0, 0},
250 { 65000000, 81250000, 3, 325, 0, 3, 3, 1, 0, 0, 10, 0, 0},
251 { 71000000, 71000000, 3, 284, 0, 3, 3, 1, 0, 0, 8, 0, 0},
252 { 71000000, 88750000, 3, 355, 0, 3, 3, 1, 0, 0, 10, 0, 0},
253 { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B},
254 { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0},
255 { 74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817},
256 { 74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0},
257 { 83500000, 83500000, 2, 167, 2, 1, 1, 1, 0, 0, 6, 0, 0},
258 { 83500000, 104375000, 1, 104, 2, 1, 1, 1, 1, 0, 5, 0, 0x600000},
259 { 85750000, 85750000, 3, 343, 0, 3, 3, 1, 0, 0, 8, 0, 0},
260 { 88750000, 88750000, 3, 355, 0, 3, 3, 1, 0, 0, 8, 0, 0},
261 { 88750000, 110937500, 1, 110, 2, 1, 1, 1, 1, 0, 5, 0, 0xF00000},
262 {108000000, 108000000, 1, 90, 3, 0, 0, 1, 0, 0, 5, 0, 0},
263 {108000000, 135000000, 1, 90, 0, 2, 2, 1, 0, 0, 5, 0, 0},
264 {119000000, 119000000, 1, 119, 2, 1, 1, 1, 0, 0, 6, 0, 0},
265 {119000000, 148750000, 1, 99, 0, 2, 2, 1, 0, 0, 5, 0, 0x2AAAAA},
266 {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B},
267 {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0},
268 {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817},
269 {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0},
270 {162000000, 162000000, 1, 108, 0, 2, 2, 1, 0, 0, 4, 0, 0},
271 {162000000, 202500000, 1, 135, 0, 2, 2, 1, 0, 0, 5, 0, 0},
272 {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B},
273 {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0},
274 {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817},
275 {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0},
276 {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B},
277 {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0},
278 {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817},
279 {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0},
280 {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B},
281 {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0},
282 { ~0UL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
283 };
284
285 static const struct post_pll_config post_pll_cfg_table[] = {
286 {33750000, 1, 40, 8, 1},
287 {33750000, 1, 80, 8, 2},
288 {33750000, 1, 10, 2, 4},
289 {74250000, 1, 40, 8, 1},
290 {74250000, 18, 80, 8, 2},
291 {74250000, 1, 20, 4, 8},
292 {148500000, 2, 40, 4, 3},
293 {148500000, 1, 10, 2, 8},
294 {297000000, 4, 40, 2, 3},
295 {297000000, 2, 20, 2, 8},
296 {594000000, 8, 40, 1, 3},
297 {594000000, 4, 20, 1, 8},
298 { ~0UL, 0, 0, 0, 0}
299 };
300
301 static const struct phy_config rk3228_phy_cfg[] = {
302 { 165000000, {
303 0xaa, 0x00, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
304 0x00, 0x00, 0x00, 0x00, 0x00,
305 },
306 }, {
307 340000000, {
308 0xaa, 0x15, 0x6a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00,
309 0x00, 0x00, 0x00, 0x00, 0x00,
310 },
311 }, {
312 594000000, {
313 0xaa, 0x15, 0x7a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00,
314 0x00, 0x00, 0x00, 0x00, 0x00,
315 },
316 }, {
317 ~0UL, {
318 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
319 0x00, 0x00, 0x00, 0x00, 0x00,
320 },
321 }
322 };
323
324 static const struct phy_config rk3328_phy_cfg[] = {
325 { 165000000, {
326 0x07, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x08, 0x08, 0x08,
327 0x00, 0xac, 0xcc, 0xcc, 0xcc,
328 },
329 }, {
330 340000000, {
331 0x0b, 0x0d, 0x0d, 0x0d, 0x07, 0x15, 0x08, 0x08, 0x08,
332 0x3f, 0xac, 0xcc, 0xcd, 0xdd,
333 },
334 }, {
335 594000000, {
336 0x10, 0x1a, 0x1a, 0x1a, 0x07, 0x15, 0x08, 0x08, 0x08,
337 0x00, 0xac, 0xcc, 0xcc, 0xcc,
338 },
339 }, {
340 ~0UL, {
341 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
342 0x00, 0x00, 0x00, 0x00, 0x00,
343 },
344 }
345 };
346
347 static const struct phy_config rk3528_phy_cfg[] = {
348 /* tmdsclk bias-clk bias-data voltage-clk voltage-data pre-emphasis-data */
349 { 165000000, {
350 0x03, 0x04, 0x0c, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00,
351 0x00, 0x00, 0x00, 0x00, 0x00,
352 },
353 }, {
354 340000000, {
355 0x03, 0x04, 0x0c, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00,
356 0x00, 0x00, 0x00, 0x00, 0x00,
357 },
358 }, {
359 594000000, {
360 0x02, 0x08, 0x0d, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
361 0x00, 0x00, 0x00, 0x00, 0x00,
362 },
363 }, {
364 ~0UL, {
365 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
366 0x00, 0x00, 0x00, 0x00, 0x00,
367 },
368 }
369 };
370
to_inno_hdmi_phy(struct clk_hw * hw)371 static inline struct inno_hdmi_phy *to_inno_hdmi_phy(struct clk_hw *hw)
372 {
373 return container_of(hw, struct inno_hdmi_phy, hw);
374 }
375
inno_write(struct inno_hdmi_phy * inno,u32 reg,u8 val)376 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val)
377 {
378 regmap_write(inno->regmap, reg * 4, val);
379 }
380
inno_read(struct inno_hdmi_phy * inno,u32 reg)381 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg)
382 {
383 u32 val;
384
385 regmap_read(inno->regmap, reg * 4, &val);
386
387 return val;
388 }
389
inno_update_bits(struct inno_hdmi_phy * inno,u8 reg,u8 mask,u8 val)390 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg,
391 u8 mask, u8 val)
392 {
393 regmap_update_bits(inno->regmap, reg * 4, mask, val);
394 }
395
inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy * inno,int rate)396 static u32 inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, int rate)
397 {
398 int bus_width = phy_get_bus_width(inno->phy);
399 u32 tmdsclk;
400
401 switch (bus_width) {
402 case 4:
403 tmdsclk = (u32)rate / 2;
404 break;
405 case 5:
406 tmdsclk = (u32)rate * 5 / 8;
407 break;
408 case 6:
409 tmdsclk = (u32)rate * 3 / 4;
410 break;
411 case 10:
412 tmdsclk = (u32)rate * 5 / 4;
413 break;
414 case 12:
415 tmdsclk = (u32)rate * 3 / 2;
416 break;
417 case 16:
418 tmdsclk = (u32)rate * 2;
419 break;
420 default:
421 tmdsclk = rate;
422 }
423
424 return tmdsclk;
425 }
426
inno_hdmi_phy_hardirq(int irq,void * dev_id)427 static irqreturn_t inno_hdmi_phy_hardirq(int irq, void *dev_id)
428 {
429 struct inno_hdmi_phy *inno = dev_id;
430 int intr_stat1, intr_stat2, intr_stat3;
431
432 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228)
433 return IRQ_NONE;
434
435 intr_stat1 = inno_read(inno, 0x04);
436 intr_stat2 = inno_read(inno, 0x06);
437 intr_stat3 = inno_read(inno, 0x08);
438
439 if (intr_stat1)
440 inno_write(inno, 0x04, intr_stat1);
441 if (intr_stat2)
442 inno_write(inno, 0x06, intr_stat2);
443 if (intr_stat3)
444 inno_write(inno, 0x08, intr_stat3);
445
446 if (intr_stat1 || intr_stat2 || intr_stat3)
447 return IRQ_WAKE_THREAD;
448
449 return IRQ_HANDLED;
450 }
451
inno_hdmi_phy_irq(int irq,void * dev_id)452 static irqreturn_t inno_hdmi_phy_irq(int irq, void *dev_id)
453 {
454 struct inno_hdmi_phy *inno = dev_id;
455
456 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228)
457 return IRQ_NONE;
458 /* set pdata_en to 0 */
459 inno_update_bits(inno, 0x02, 1, 0);
460
461 udelay(10);
462
463 /* set pdata_en to 1 */
464 inno_update_bits(inno, 0x02, 1, 1);
465
466 return IRQ_HANDLED;
467 }
468
469 static int inno_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
470 unsigned long parent_rate);
471
inno_hdmi_phy_power_on(struct phy * phy)472 static int inno_hdmi_phy_power_on(struct phy *phy)
473 {
474 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
475 const struct post_pll_config *cfg = post_pll_cfg_table;
476 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;
477 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock);
478 u32 chipversion = 1;
479
480 if (inno->phy_cfg)
481 phy_cfg = inno->phy_cfg;
482
483 if (!tmdsclock) {
484 dev_err(inno->dev, "TMDS clock is zero!\n");
485 return -EINVAL;
486 }
487
488 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3328 &&
489 rockchip_get_cpu_version())
490 chipversion = 2;
491 else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 &&
492 tmdsclock <= 33750000 && inno->efuse_flag)
493 chipversion = 4;
494 else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3528)
495 chipversion = 8;
496
497 for (; cfg->tmdsclock != ~0UL; cfg++)
498 if (tmdsclock <= cfg->tmdsclock &&
499 cfg->version & chipversion)
500 break;
501
502 for (; phy_cfg->tmdsclock != ~0UL; phy_cfg++)
503 if (tmdsclock <= phy_cfg->tmdsclock)
504 break;
505
506 if (cfg->tmdsclock == ~0UL || phy_cfg->tmdsclock == ~0UL)
507 return -EINVAL;
508
509 dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");
510 inno_hdmi_phy_clk_set_rate(&inno->hw, inno->pixclock, 0);
511
512 if (inno->plat_data->ops->power_on)
513 return inno->plat_data->ops->power_on(inno, cfg, phy_cfg);
514 else
515 return -EINVAL;
516 }
517
inno_hdmi_phy_power_off(struct phy * phy)518 static int inno_hdmi_phy_power_off(struct phy *phy)
519 {
520 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
521
522 if (inno->plat_data->ops->power_off)
523 inno->plat_data->ops->power_off(inno);
524
525 inno->tmdsclock = 0;
526 dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
527
528 return 0;
529 }
530
531 static const struct phy_ops inno_hdmi_phy_ops = {
532 .owner = THIS_MODULE,
533 .power_on = inno_hdmi_phy_power_on,
534 .power_off = inno_hdmi_phy_power_off,
535 };
536
inno_hdmi_phy_clk_is_prepared(struct clk_hw * hw)537 static int inno_hdmi_phy_clk_is_prepared(struct clk_hw *hw)
538 {
539 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
540 u8 status;
541
542 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228)
543 status = inno_read(inno, 0xe0) & PRE_PLL_POWER_MASK;
544 else
545 status = inno_read(inno, 0xa0) & 1;
546
547 return status ? 0 : 1;
548 }
549
inno_hdmi_phy_clk_prepare(struct clk_hw * hw)550 static int inno_hdmi_phy_clk_prepare(struct clk_hw *hw)
551 {
552 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
553
554 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228)
555 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK,
556 PRE_PLL_POWER_UP);
557 else
558 inno_update_bits(inno, 0xa0, 1, 0);
559
560 return 0;
561 }
562
inno_hdmi_phy_clk_unprepare(struct clk_hw * hw)563 static void inno_hdmi_phy_clk_unprepare(struct clk_hw *hw)
564 {
565 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
566
567 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228)
568 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK,
569 PRE_PLL_POWER_DOWN);
570 else
571 inno_update_bits(inno, 0xa0, 1, 1);
572 }
573
inno_hdmi_phy_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)574 static unsigned long inno_hdmi_phy_clk_recalc_rate(struct clk_hw *hw,
575 unsigned long parent_rate)
576 {
577 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
578
579 if (inno->plat_data->ops->recalc_rate)
580 return inno->plat_data->ops->recalc_rate(inno, parent_rate);
581 else
582 return inno->pixclock;
583 }
584
inno_hdmi_phy_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)585 static long inno_hdmi_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
586 unsigned long *parent_rate)
587 {
588 int i;
589 const struct pre_pll_config *cfg = pre_pll_cfg_table;
590 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
591 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
592
593 for (; cfg->pixclock != ~0UL; cfg++)
594 if (cfg->pixclock == rate)
595 break;
596
597 /* XXX: Limit pixel clock under 600MHz */
598 if (cfg->pixclock > 600000000)
599 return -EINVAL;
600
601 /*
602 * If there is no dts phy cfg table, use default phy cfg table.
603 * The tmds clock maximum is 594MHz. So there is no need to check
604 * whether tmds clock is out of range.
605 */
606 if (!inno->phy_cfg)
607 return cfg->pixclock;
608
609 /* Check if tmds clock is out of dts phy config's range. */
610 for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) {
611 if (inno->phy_cfg[i].tmdsclock >= tmdsclock)
612 break;
613 }
614
615 if (inno->phy_cfg[i].tmdsclock == ~0UL)
616 return -EINVAL;
617
618 return cfg->pixclock;
619 }
620
inno_hdmi_phy_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)621 static int inno_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
622 unsigned long parent_rate)
623 {
624 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
625 const struct pre_pll_config *cfg = pre_pll_cfg_table;
626 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
627
628 dev_dbg(inno->dev, "%s rate %lu tmdsclk %u\n",
629 __func__, rate, tmdsclock);
630
631 if (inno->tmdsclock == tmdsclock)
632 return 0;
633
634 for (; cfg->pixclock != ~0UL; cfg++)
635 if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock)
636 break;
637
638 if (cfg->pixclock == ~0UL) {
639 dev_err(inno->dev, "unsupported rate %lu\n", rate);
640 return -EINVAL;
641 }
642
643 if (inno->plat_data->ops->pre_pll_update)
644 inno->plat_data->ops->pre_pll_update(inno, cfg);
645
646 inno->pixclock = rate;
647 inno->tmdsclock = tmdsclock;
648
649 return 0;
650 }
651
652 static const struct clk_ops inno_hdmi_phy_clk_ops = {
653 .prepare = inno_hdmi_phy_clk_prepare,
654 .unprepare = inno_hdmi_phy_clk_unprepare,
655 .is_prepared = inno_hdmi_phy_clk_is_prepared,
656 .recalc_rate = inno_hdmi_phy_clk_recalc_rate,
657 .round_rate = inno_hdmi_phy_clk_round_rate,
658 .set_rate = inno_hdmi_phy_clk_set_rate,
659 };
660
inno_hdmi_phy_clk_register(struct inno_hdmi_phy * inno)661 static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno)
662 {
663 struct device *dev = inno->dev;
664 struct device_node *np = dev->of_node;
665 struct device_node *clk_np = NULL;
666 struct clk_init_data init = {};
667 struct clk *refclk;
668 const char *parent_name;
669 int ret;
670
671 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3528)
672 clk_np = of_get_child_by_name(np, "clk-port");
673
674 if (!clk_np)
675 clk_np = np;
676
677 refclk = devm_clk_get(dev, "refclk");
678 if (IS_ERR(refclk)) {
679 dev_err(dev, "failed to get ref clock\n");
680 return PTR_ERR(refclk);
681 }
682
683 parent_name = __clk_get_name(refclk);
684
685 init.parent_names = &parent_name;
686 init.num_parents = 1;
687 init.flags = 0;
688 init.name = "pin_hd20_pclk";
689 init.ops = &inno_hdmi_phy_clk_ops;
690
691 /* optional override of the clock name */
692 of_property_read_string(clk_np, "clock-output-names", &init.name);
693
694 inno->hw.init = &init;
695
696 inno->pclk = devm_clk_register(dev, &inno->hw);
697 if (IS_ERR(inno->pclk)) {
698 ret = PTR_ERR(inno->pclk);
699 dev_err(dev, "failed to register clock: %d\n", ret);
700 return ret;
701 }
702
703 ret = of_clk_add_provider(clk_np, of_clk_src_simple_get, inno->pclk);
704 if (ret) {
705 dev_err(dev, "failed to register OF clock provider: %d\n", ret);
706 return ret;
707 }
708
709 return 0;
710 }
711
712 static int
inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy * inno,const struct post_pll_config * cfg,const struct phy_config * phy_cfg)713 inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno,
714 const struct post_pll_config *cfg,
715 const struct phy_config *phy_cfg)
716 {
717 int pll_tries;
718 u32 m, v;
719
720 /* pdata_en disable */
721 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_DISABLE);
722
723 /* Power down Post-PLL */
724 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN);
725 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN);
726
727 /* Post-PLL update */
728 m = POST_PLL_PRE_DIV_MASK;
729 v = POST_PLL_PRE_DIV(cfg->prediv);
730 inno_update_bits(inno, 0xe9, m, v);
731
732 m = POST_PLL_FB_DIV_8_MASK;
733 v = POST_PLL_FB_DIV_8(cfg->fbdiv >> 8);
734 inno_update_bits(inno, 0xeb, m, v);
735 inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv));
736
737 if (cfg->postdiv == 1) {
738 /* Disable Post-PLL post divider */
739 m = POST_PLL_POST_DIV_EN_MASK;
740 v = POST_PLL_POST_DIV_DISABLE;
741 inno_update_bits(inno, 0xe9, m, v);
742 } else {
743 /* Enable Post-PLL post divider */
744 m = POST_PLL_POST_DIV_EN_MASK;
745 v = POST_PLL_POST_DIV_ENABLE;
746 inno_update_bits(inno, 0xe9, m, v);
747
748 m = POST_PLL_POST_DIV_MASK;
749 v = POST_PLL_POST_DIV(cfg->postdiv / 2 - 1);
750 inno_update_bits(inno, 0xeb, m, v);
751 }
752
753 for (v = 0; v < 4; v++)
754 inno_write(inno, 0xef + v, phy_cfg->regs[v]);
755
756 /* Power up Post-PLL */
757 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_UP);
758 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP);
759
760 /* BandGap enable */
761 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_ENABLE);
762
763 /* TMDS driver enable */
764 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_ENABLE);
765
766 /* Wait for post PLL lock */
767 pll_tries = 0;
768 while (!(inno_read(inno, 0xeb) & POST_PLL_LOCK_STATUS)) {
769 if (pll_tries == INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT) {
770 dev_err(inno->dev, "Post-PLL unlock\n");
771 return -ETIMEDOUT;
772 }
773
774 pll_tries++;
775 usleep_range(100, 110);
776 }
777
778 if (cfg->tmdsclock > 340000000)
779 msleep(100);
780
781 /* pdata_en enable */
782 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_ENABLE);
783 return 0;
784 }
785
inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy * inno)786 static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno)
787 {
788 /* TMDS driver Disable */
789 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_DISABLE);
790
791 /* BandGap Disable */
792 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_DISABLE);
793
794 /* Post-PLL power down */
795 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN);
796 }
797
inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy * inno)798 static void inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
799 {
800 u32 m, v;
801 struct nvmem_cell *cell;
802 unsigned char *efuse_buf;
803 size_t len;
804
805 /*
806 * Use phy internal register control
807 * rxsense/poweron/pllpd/pdataen signal.
808 */
809 m = BYPASS_RXSENSE_EN_MASK | BYPASS_PWRON_EN_MASK |
810 BYPASS_PLLPD_EN_MASK;
811 v = BYPASS_RXSENSE_EN | BYPASS_PWRON_EN | BYPASS_PLLPD_EN;
812 inno_update_bits(inno, 0x01, m, v);
813 inno_update_bits(inno, 0x02, BYPASS_PDATA_EN_MASK, BYPASS_PDATA_EN);
814
815 /*
816 * reg0xe9 default value is 0xe4, reg0xea is 0x50.
817 * if phy had been set in uboot, one of them will be different.
818 */
819 if ((inno_read(inno, 0xe9) != 0xe4 || inno_read(inno, 0xea) != 0x50)) {
820 dev_info(inno->dev, "phy had been powered up\n");
821 inno->phy->power_count = 1;
822 } else {
823 inno_hdmi_phy_rk3228_power_off(inno);
824 /* manual power down post-PLL */
825 inno_update_bits(inno, 0xaa,
826 POST_PLL_CTRL_MASK, POST_PLL_CTRL_MANUAL);
827 }
828
829 cell = nvmem_cell_get(inno->dev, "hdmi_phy_flag");
830 if (IS_ERR(cell)) {
831 dev_err(inno->dev,
832 "failed to get id cell: %ld\n", PTR_ERR(cell));
833 return;
834 }
835 efuse_buf = nvmem_cell_read(cell, &len);
836 nvmem_cell_put(cell);
837 if (len == 1)
838 inno->efuse_flag = efuse_buf[0] ? true : false;
839 kfree(efuse_buf);
840 }
841
842 static int
inno_hdmi_phy_rk3228_pre_pll_update(struct inno_hdmi_phy * inno,const struct pre_pll_config * cfg)843 inno_hdmi_phy_rk3228_pre_pll_update(struct inno_hdmi_phy *inno,
844 const struct pre_pll_config *cfg)
845 {
846 int pll_tries;
847 u32 m, v;
848
849 /* Power down PRE-PLL */
850 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN);
851
852 m = PRE_PLL_FB_DIV_8_MASK | PCLK_VCO_DIV_5_MASK | PRE_PLL_PRE_DIV_MASK;
853 v = PRE_PLL_FB_DIV_8(cfg->fbdiv >> 8) |
854 PCLK_VCO_DIV_5(cfg->vco_div_5_en) | PRE_PLL_PRE_DIV(cfg->prediv);
855 inno_update_bits(inno, 0xe2, m, v);
856
857 inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
858
859 m = PRE_PLL_PCLK_DIV_B_MASK | PRE_PLL_PCLK_DIV_A_MASK;
860 v = PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) |
861 PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a);
862 inno_update_bits(inno, 0xe4, m, v);
863
864 m = PRE_PLL_PCLK_DIV_C_MASK | PRE_PLL_PCLK_DIV_D_MASK;
865 v = PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) |
866 PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d);
867 inno_update_bits(inno, 0xe5, m, v);
868
869 m = PRE_PLL_TMDSCLK_DIV_C_MASK | PRE_PLL_TMDSCLK_DIV_A_MASK |
870 PRE_PLL_TMDSCLK_DIV_B_MASK;
871 v = PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |
872 PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) |
873 PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b);
874 inno_update_bits(inno, 0xe6, m, v);
875
876 /* Power up PRE-PLL */
877 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP);
878
879 /* Wait for Pre-PLL lock */
880 pll_tries = 0;
881 while (!(inno_read(inno, 0xe8) & PRE_PLL_LOCK_STATUS)) {
882 if (pll_tries == INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT) {
883 dev_err(inno->dev, "Pre-PLL unlock\n");
884 return -ETIMEDOUT;
885 }
886
887 pll_tries++;
888 usleep_range(100, 110);
889 }
890
891 return 0;
892 }
893
894 static int
inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy * inno,const struct post_pll_config * cfg,const struct phy_config * phy_cfg)895 inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,
896 const struct post_pll_config *cfg,
897 const struct phy_config *phy_cfg)
898 {
899 u32 val;
900 u64 temp;
901
902 /* set pdata_en to 0 */
903 inno_update_bits(inno, 0x02, 1, 0);
904 /* Power off post PLL */
905 inno_update_bits(inno, 0xaa, 1, 1);
906
907 val = cfg->fbdiv & 0xff;
908 inno_write(inno, 0xac, val);
909 if (cfg->postdiv == 1) {
910 inno_write(inno, 0xaa, 2);
911 val = (cfg->fbdiv >> 8) | cfg->prediv;
912 inno_write(inno, 0xab, val);
913 } else {
914 val = (cfg->postdiv / 2) - 1;
915 inno_write(inno, 0xad, val);
916 val = (cfg->fbdiv >> 8) | cfg->prediv;
917 inno_write(inno, 0xab, val);
918 inno_write(inno, 0xaa, 0x0e);
919 }
920
921 for (val = 0; val < 14; val++)
922 inno_write(inno, 0xb5 + val, phy_cfg->regs[val]);
923
924 /* bit[7:6] of reg c8/c9/ca/c8 is ESD detect threshold:
925 * 00 - 340mV
926 * 01 - 280mV
927 * 10 - 260mV
928 * 11 - 240mV
929 * default is 240mV, now we set it to 340mV
930 */
931 inno_write(inno, 0xc8, 0);
932 inno_write(inno, 0xc9, 0);
933 inno_write(inno, 0xca, 0);
934 inno_write(inno, 0xcb, 0);
935
936 if (phy_cfg->tmdsclock > 340000000) {
937 /* Set termination resistor to 100ohm */
938 val = clk_get_rate(inno->sysclk) / 100000;
939 inno_write(inno, 0xc5, ((val >> 8) & 0xff) | 0x80);
940 inno_write(inno, 0xc6, val & 0xff);
941 inno_write(inno, 0xc7, 3 << 1);
942 inno_write(inno, 0xc5, ((val >> 8) & 0xff));
943 } else {
944 inno_write(inno, 0xc5, 0x81);
945 /* clk termination resistor is 50ohm */
946 if (phy_cfg->tmdsclock > 165000000)
947 inno_write(inno, 0xc8, 0x30);
948 /* data termination resistor is 150ohm */
949 inno_write(inno, 0xc9, 0x10);
950 inno_write(inno, 0xca, 0x10);
951 inno_write(inno, 0xcb, 0x10);
952 }
953
954 /* set TMDS sync detection counter length */
955 temp = 47520000000;
956 do_div(temp, inno->tmdsclock);
957 inno_write(inno, 0xd8, (temp >> 8) & 0xff);
958 inno_write(inno, 0xd9, temp & 0xff);
959
960 /* Power up post PLL */
961 inno_update_bits(inno, 0xaa, 1, 0);
962 /* Power up tmds driver */
963 inno_update_bits(inno, 0xb0, 4, 4);
964 inno_write(inno, 0xb2, 0x0f);
965
966 /* Wait for post PLL lock */
967 for (val = 0; val < 5; val++) {
968 if (inno_read(inno, 0xaf) & 1)
969 break;
970 usleep_range(1000, 2000);
971 }
972 if (!(inno_read(inno, 0xaf) & 1)) {
973 dev_err(inno->dev, "HDMI PHY Post PLL unlock\n");
974 return -ETIMEDOUT;
975 }
976 if (phy_cfg->tmdsclock > 340000000)
977 msleep(100);
978 /* set pdata_en to 1 */
979 inno_update_bits(inno, 0x02, 1, 1);
980
981 /* Enable PHY IRQ */
982 inno_write(inno, 0x05, 0x22);
983 inno_write(inno, 0x07, 0x22);
984 return 0;
985 }
986
inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy * inno)987 static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno)
988 {
989 /* Power off driver */
990 inno_write(inno, 0xb2, 0);
991 /* Power off band gap */
992 inno_update_bits(inno, 0xb0, 4, 0);
993 /* Power off post pll */
994 inno_update_bits(inno, 0xaa, 1, 1);
995
996 /* Disable PHY IRQ */
997 inno_write(inno, 0x05, 0);
998 inno_write(inno, 0x07, 0);
999 }
1000
inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy * inno)1001 static void inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)
1002 {
1003 /*
1004 * Use phy internal register control
1005 * rxsense/poweron/pllpd/pdataen signal.
1006 */
1007 inno_write(inno, 0x01, 0x07);
1008 inno_write(inno, 0x02, 0x91);
1009
1010 /*
1011 * reg0xc8 default value is 0xc0, if phy had been set in uboot,
1012 * the value of bit[7:6] will be zero.
1013 */
1014 if ((inno_read(inno, 0xc8) & 0xc0) == 0) {
1015 dev_info(inno->dev, "phy had been powered up\n");
1016 inno->phy->power_count = 1;
1017 } else {
1018 /* manual power down post-PLL */
1019 inno_hdmi_phy_rk3328_power_off(inno);
1020 }
1021 }
1022
1023 static int
inno_hdmi_phy_rk3328_pre_pll_update(struct inno_hdmi_phy * inno,const struct pre_pll_config * cfg)1024 inno_hdmi_phy_rk3328_pre_pll_update(struct inno_hdmi_phy *inno,
1025 const struct pre_pll_config *cfg)
1026 {
1027 u32 val;
1028
1029 /* Power off PLL */
1030 inno_update_bits(inno, 0xa0, 1, 1);
1031 /* Configure pre-pll */
1032 inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1);
1033 inno_write(inno, 0xa1, cfg->prediv);
1034 if (cfg->fracdiv)
1035 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0;
1036 else
1037 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xf0;
1038 inno_write(inno, 0xa2, val);
1039 inno_write(inno, 0xa3, cfg->fbdiv & 0xff);
1040 val = (cfg->pclk_div_a & 0x1f) |
1041 ((cfg->pclk_div_b & 3) << 5);
1042 inno_write(inno, 0xa5, val);
1043 val = (cfg->pclk_div_d & 0x1f) |
1044 ((cfg->pclk_div_c & 3) << 5);
1045 inno_write(inno, 0xa6, val);
1046 val = ((cfg->tmds_div_a & 3) << 4) |
1047 ((cfg->tmds_div_b & 3) << 2) |
1048 (cfg->tmds_div_c & 3);
1049 inno_write(inno, 0xa4, val);
1050
1051 if (cfg->fracdiv) {
1052 val = cfg->fracdiv & 0xff;
1053 inno_write(inno, 0xd3, val);
1054 val = (cfg->fracdiv >> 8) & 0xff;
1055 inno_write(inno, 0xd2, val);
1056 val = (cfg->fracdiv >> 16) & 0xff;
1057 inno_write(inno, 0xd1, val);
1058 } else {
1059 inno_write(inno, 0xd3, 0);
1060 inno_write(inno, 0xd2, 0);
1061 inno_write(inno, 0xd1, 0);
1062 }
1063
1064 /* Power up PLL */
1065 inno_update_bits(inno, 0xa0, 1, 0);
1066
1067 /* Wait for PLL lock */
1068 for (val = 0; val < 5; val++) {
1069 if (inno_read(inno, 0xa9) & 1)
1070 break;
1071 usleep_range(1000, 2000);
1072 }
1073 if (val == 5) {
1074 dev_err(inno->dev, "Pre-PLL unlock\n");
1075 return -ETIMEDOUT;
1076 }
1077
1078 return 0;
1079 }
1080
1081 static unsigned long
inno_hdmi_rk3328_phy_pll_recalc_rate(struct inno_hdmi_phy * inno,unsigned long parent_rate)1082 inno_hdmi_rk3328_phy_pll_recalc_rate(struct inno_hdmi_phy *inno,
1083 unsigned long parent_rate)
1084 {
1085 unsigned long frac;
1086 u8 nd, no_a, no_b, no_d;
1087 u16 nf;
1088 u64 vco = parent_rate;
1089
1090 nd = inno_read(inno, 0xa1) & 0x3f;
1091 nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3);
1092 vco *= nf;
1093 if ((inno_read(inno, 0xa2) & 0x30) == 0) {
1094 frac = inno_read(inno, 0xd3) |
1095 (inno_read(inno, 0xd2) << 8) |
1096 (inno_read(inno, 0xd1) << 16);
1097 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24));
1098 }
1099 if (inno_read(inno, 0xa0) & 2) {
1100 do_div(vco, nd * 5);
1101 } else {
1102 no_a = inno_read(inno, 0xa5) & 0x1f;
1103 no_b = ((inno_read(inno, 0xa5) >> 5) & 7) + 2;
1104 no_d = inno_read(inno, 0xa6) & 0x1f;
1105 if (no_a == 1)
1106 do_div(vco, nd * no_b * no_d * 2);
1107 else
1108 do_div(vco, nd * no_a * no_d * 2);
1109 }
1110
1111 frac = vco;
1112 inno->pixclock = DIV_ROUND_CLOSEST(frac, 1000) * 1000;
1113
1114 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
1115
1116 return frac;
1117 }
1118
1119 static int
inno_hdmi_phy_rk3528_power_on(struct inno_hdmi_phy * inno,const struct post_pll_config * cfg,const struct phy_config * phy_cfg)1120 inno_hdmi_phy_rk3528_power_on(struct inno_hdmi_phy *inno,
1121 const struct post_pll_config *cfg,
1122 const struct phy_config *phy_cfg)
1123 {
1124 u32 val;
1125 u64 temp;
1126
1127 /* Power off post PLL */
1128 inno_update_bits(inno, 0xaa, 1, 0);
1129
1130 val = cfg->prediv;
1131 inno_write(inno, 0xab, val);
1132
1133 if (cfg->postdiv == 1) {
1134 inno_write(inno, 0xad, 0x8);
1135 inno_write(inno, 0xaa, 2);
1136 } else {
1137 val = (cfg->postdiv / 2) - 1;
1138 inno_write(inno, 0xad, val);
1139 inno_write(inno, 0xaa, 0x0e);
1140 }
1141
1142 val = cfg->fbdiv & 0xff;
1143 inno_write(inno, 0xac, val);
1144 val = (cfg->fbdiv >> 8) & BIT(0);
1145 inno_update_bits(inno, 0xad, BIT(4), val);
1146
1147 /* current bias clk/data 2 */
1148 val = phy_cfg->regs[0] << 4 | phy_cfg->regs[1];
1149 inno_write(inno, 0xbf, val);
1150
1151 /* current bias data 1/0 */
1152 val = phy_cfg->regs[1] << 4 | phy_cfg->regs[1];
1153 inno_write(inno, 0xc0, val);
1154
1155 /* output voltage */
1156 inno_write(inno, 0xb5, phy_cfg->regs[2]);
1157 inno_write(inno, 0xb6, phy_cfg->regs[3]);
1158 inno_write(inno, 0xb7, phy_cfg->regs[3]);
1159 inno_write(inno, 0xb8, phy_cfg->regs[3]);
1160
1161 /* pre-emphasis */
1162 inno_write(inno, 0xbb, phy_cfg->regs[4]);
1163 inno_write(inno, 0xbc, phy_cfg->regs[4]);
1164 inno_write(inno, 0xbd, phy_cfg->regs[4]);
1165
1166 /* enable LDO */
1167 inno_write(inno, 0xb4, 0x7);
1168
1169 /* enable serializer */
1170 inno_write(inno, 0xbe, 0x70);
1171
1172 inno_write(inno, 0xb2, 0x0f);
1173
1174 for (val = 0; val < 5; val++) {
1175 if (inno_read(inno, 0xaf) & 1)
1176 break;
1177 udelay(1000);
1178 }
1179 if (!(inno_read(inno, 0xaf) & 1)) {
1180 dev_err(inno->dev, "HDMI PHY Post PLL unlock\n");
1181 return -ETIMEDOUT;
1182 }
1183
1184 /* set termination resistance */
1185 if (phy_cfg->tmdsclock > 340000000) {
1186 inno_write(inno, 0xc7, 0x76);
1187 inno_write(inno, 0xc5, 0x83);
1188 inno_write(inno, 0xc8, 0x00);
1189 inno_write(inno, 0xc9, 0x2f);
1190 inno_write(inno, 0xca, 0x2f);
1191 inno_write(inno, 0xcb, 0x2f);
1192 } else {
1193 inno_write(inno, 0xc7, 0x76);
1194 inno_write(inno, 0xc5, 0x83);
1195 inno_write(inno, 0xc8, 0x00);
1196 inno_write(inno, 0xc9, 0x0f);
1197 inno_write(inno, 0xca, 0x0f);
1198 inno_write(inno, 0xcb, 0x0f);
1199 }
1200
1201 /* set TMDS sync detection counter length */
1202 temp = 47520000000;
1203 do_div(temp, inno->tmdsclock);
1204 inno_write(inno, 0xd8, (temp >> 8) & 0xff);
1205 inno_write(inno, 0xd9, temp & 0xff);
1206
1207 /* Power up post PLL */
1208 inno_update_bits(inno, 0xaa, 1, 0);
1209 /* Power up tmds driver */
1210 inno_update_bits(inno, 0xb0, 4, 4);
1211 inno_write(inno, 0xb2, 0x0f);
1212
1213 if (phy_cfg->tmdsclock > 340000000)
1214 msleep(100);
1215 /* set pdata_en to 0/1 */
1216 inno_update_bits(inno, 0x02, 1, 0);
1217 inno_update_bits(inno, 0x02, 1, 1);
1218
1219 /* Enable PHY IRQ */
1220 inno_write(inno, 0x05, 0x22);
1221 inno_write(inno, 0x07, 0x22);
1222 inno_write(inno, 0xcc, 0x0f);
1223
1224 return 0;
1225 }
1226
inno_hdmi_phy_rk3528_power_off(struct inno_hdmi_phy * inno)1227 static void inno_hdmi_phy_rk3528_power_off(struct inno_hdmi_phy *inno)
1228 {
1229 /* Power off driver */
1230 inno_write(inno, 0xb2, 0);
1231 /* Power off serializer */
1232 inno_write(inno, 0xbe, 0);
1233 /* Power off post pll */
1234 inno_update_bits(inno, 0xaa, 1, 1);
1235 /* Power off rxsense detection circuit */
1236 inno_write(inno, 0xcc, 0);
1237 /* Power off band gap */
1238 inno_update_bits(inno, 0xb0, 4, 0);
1239 /* Disable PHY IRQ */
1240 inno_write(inno, 0x05, 0);
1241 inno_write(inno, 0x07, 0);
1242 }
1243
inno_hdmi_phy_rk3528_init(struct inno_hdmi_phy * inno)1244 static void inno_hdmi_phy_rk3528_init(struct inno_hdmi_phy *inno)
1245 {
1246 /*
1247 * Use phy internal register control
1248 * rxsense/poweron/pllpd/pdataen signal.
1249 */
1250 inno_write(inno, 0x02, 0x81);
1251
1252 /* if phy had been set in uboot, pll is locked */
1253 if (inno_read(inno, 0xa9) & BIT(0)) {
1254 dev_info(inno->dev, "phy had been powered up\n");
1255 inno->phy->power_count = 1;
1256 } else {
1257 /* manual power down post-PLL */
1258 inno_hdmi_phy_rk3528_power_off(inno);
1259 }
1260 }
1261
1262 static int
inno_hdmi_phy_rk3528_pre_pll_update(struct inno_hdmi_phy * inno,const struct pre_pll_config * cfg)1263 inno_hdmi_phy_rk3528_pre_pll_update(struct inno_hdmi_phy *inno,
1264 const struct pre_pll_config *cfg)
1265 {
1266 u32 val;
1267
1268 inno_update_bits(inno, 0xb0, 4, 4);
1269 inno_write(inno, 0xcc, 0x0f);
1270
1271 /* Power on PLL */
1272 inno_update_bits(inno, 0xa0, 1, 0);
1273 /* Configure pre-pll */
1274 inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1);
1275 inno_write(inno, 0xa1, cfg->prediv);
1276 if (cfg->fracdiv)
1277 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0;
1278 else
1279 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xf0;
1280 inno_write(inno, 0xa2, val);
1281 inno_write(inno, 0xa3, cfg->fbdiv & 0xff);
1282 val = (cfg->pclk_div_a & 0x1f) |
1283 ((cfg->pclk_div_b & 3) << 5);
1284 inno_write(inno, 0xa5, val);
1285 val = (cfg->pclk_div_d & 0x1f) |
1286 ((cfg->pclk_div_c & 3) << 5);
1287 inno_write(inno, 0xa6, val);
1288 val = ((cfg->tmds_div_a & 3) << 4) |
1289 ((cfg->tmds_div_b & 3) << 2) |
1290 (cfg->tmds_div_c & 3);
1291 inno_write(inno, 0xa4, val);
1292
1293 if (cfg->fracdiv) {
1294 val = cfg->fracdiv & 0xff;
1295 inno_write(inno, 0xd3, val);
1296 val = (cfg->fracdiv >> 8) & 0xff;
1297 inno_write(inno, 0xd2, val);
1298 val = (cfg->fracdiv >> 16) & 0xff;
1299 inno_write(inno, 0xd1, val);
1300 } else {
1301 inno_write(inno, 0xd3, 0);
1302 inno_write(inno, 0xd2, 0);
1303 inno_write(inno, 0xd1, 0);
1304 }
1305
1306 /* Wait for PLL lock */
1307 for (val = 0; val < 5; val++) {
1308 if (inno_read(inno, 0xa9) & 1)
1309 break;
1310 usleep_range(1000, 2000);
1311 }
1312 if (val == 5) {
1313 dev_err(inno->dev, "Pre-PLL unlock\n");
1314 return -ETIMEDOUT;
1315 }
1316
1317 return 0;
1318 }
1319
1320 static unsigned long
inno_hdmi_rk3528_phy_pll_recalc_rate(struct inno_hdmi_phy * inno,unsigned long parent_rate)1321 inno_hdmi_rk3528_phy_pll_recalc_rate(struct inno_hdmi_phy *inno,
1322 unsigned long parent_rate)
1323 {
1324 unsigned long frac;
1325 u8 nd, no_a, no_b, no_d;
1326 u16 nf;
1327 u64 vco = parent_rate;
1328
1329 nd = inno_read(inno, 0xa1) & 0x3f;
1330 nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3);
1331 vco *= nf;
1332 if ((inno_read(inno, 0xa2) & 0x30) == 0) {
1333 frac = inno_read(inno, 0xd3) |
1334 (inno_read(inno, 0xd2) << 8) |
1335 (inno_read(inno, 0xd1) << 16);
1336 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24));
1337 }
1338 if (inno_read(inno, 0xa0) & 2) {
1339 do_div(vco, nd * 5);
1340 } else {
1341 no_a = inno_read(inno, 0xa5) & 0x1f;
1342 no_b = ((inno_read(inno, 0xa5) >> 5) & 7) + 2;
1343 no_d = inno_read(inno, 0xa6) & 0x1f;
1344 if (no_a == 1)
1345 do_div(vco, nd * no_b * no_d * 2);
1346 else
1347 do_div(vco, nd * no_a * no_d * 2);
1348 }
1349
1350 frac = vco;
1351 inno->pixclock = DIV_ROUND_CLOSEST(frac, 1000) * 1000;
1352
1353 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
1354
1355 return frac;
1356 }
1357
1358 static unsigned long
inno_hdmi_rk3228_phy_pll_recalc_rate(struct inno_hdmi_phy * inno,unsigned long parent_rate)1359 inno_hdmi_rk3228_phy_pll_recalc_rate(struct inno_hdmi_phy *inno,
1360 unsigned long parent_rate)
1361 {
1362 u8 nd, no_a, no_b, no_d;
1363 u16 nf;
1364 u64 vco = parent_rate;
1365
1366 nd = inno_read(inno, 0xe2) & 0x1f;
1367 nf = ((inno_read(inno, 0xe2) & 0x80) << 1) | inno_read(inno, 0xe3);
1368 vco *= nf;
1369
1370 if ((inno_read(inno, 0xe2) >> 5) & 0x1) {
1371 do_div(vco, nd * 5);
1372 } else {
1373 no_a = inno_read(inno, 0xe4) & 0x1f;
1374 if (!no_a)
1375 no_a = 1;
1376 no_b = ((inno_read(inno, 0xe4) >> 5) & 0x3) + 2;
1377 no_d = inno_read(inno, 0xe5) & 0x1f;
1378
1379 if (no_a == 1)
1380 do_div(vco, nd * no_b * no_d * 2);
1381 else
1382 do_div(vco, nd * no_a * no_d * 2);
1383 }
1384
1385 inno->pixclock = vco;
1386
1387 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
1388
1389 return inno->pixclock;
1390 }
1391
1392 static const struct inno_hdmi_phy_ops rk3228_hdmi_phy_ops = {
1393 .init = inno_hdmi_phy_rk3228_init,
1394 .power_on = inno_hdmi_phy_rk3228_power_on,
1395 .power_off = inno_hdmi_phy_rk3228_power_off,
1396 .pre_pll_update = inno_hdmi_phy_rk3228_pre_pll_update,
1397 .recalc_rate = inno_hdmi_rk3228_phy_pll_recalc_rate,
1398 };
1399
1400 static const struct inno_hdmi_phy_ops rk3328_hdmi_phy_ops = {
1401 .init = inno_hdmi_phy_rk3328_init,
1402 .power_on = inno_hdmi_phy_rk3328_power_on,
1403 .power_off = inno_hdmi_phy_rk3328_power_off,
1404 .pre_pll_update = inno_hdmi_phy_rk3328_pre_pll_update,
1405 .recalc_rate = inno_hdmi_rk3328_phy_pll_recalc_rate,
1406 };
1407
1408 static const struct inno_hdmi_phy_ops rk3528_hdmi_phy_ops = {
1409 .init = inno_hdmi_phy_rk3528_init,
1410 .power_on = inno_hdmi_phy_rk3528_power_on,
1411 .power_off = inno_hdmi_phy_rk3528_power_off,
1412 .pre_pll_update = inno_hdmi_phy_rk3528_pre_pll_update,
1413 .recalc_rate = inno_hdmi_rk3528_phy_pll_recalc_rate,
1414 };
1415
1416 static const struct inno_hdmi_phy_drv_data rk3228_hdmi_phy_drv_data = {
1417 .dev_type = INNO_HDMI_PHY_RK3228,
1418 .ops = &rk3228_hdmi_phy_ops,
1419 .phy_cfg_table = rk3228_phy_cfg,
1420 };
1421
1422 static const struct inno_hdmi_phy_drv_data rk3328_hdmi_phy_drv_data = {
1423 .dev_type = INNO_HDMI_PHY_RK3328,
1424 .ops = &rk3328_hdmi_phy_ops,
1425 .phy_cfg_table = rk3328_phy_cfg,
1426 };
1427
1428 static const struct inno_hdmi_phy_drv_data rk3528_hdmi_phy_drv_data = {
1429 .dev_type = INNO_HDMI_PHY_RK3528,
1430 .ops = &rk3528_hdmi_phy_ops,
1431 .phy_cfg_table = rk3528_phy_cfg,
1432 };
1433
1434 static const struct of_device_id inno_hdmi_phy_of_match[] = {
1435 { .compatible = "rockchip,rk3228-hdmi-phy",
1436 .data = &rk3228_hdmi_phy_drv_data
1437 },
1438 { .compatible = "rockchip,rk3328-hdmi-phy",
1439 .data = &rk3328_hdmi_phy_drv_data
1440 },
1441 { .compatible = "rockchip,rk3528-hdmi-phy",
1442 .data = &rk3528_hdmi_phy_drv_data
1443 },
1444 {}
1445 };
1446 MODULE_DEVICE_TABLE(of, inno_hdmi_phy_of_match);
1447
1448 static const struct regmap_config inno_hdmi_phy_regmap_config = {
1449 .reg_bits = 32,
1450 .val_bits = 32,
1451 .reg_stride = 4,
1452 .max_register = 0x400,
1453 };
1454
1455 static
inno_hdmi_update_phy_table(struct inno_hdmi_phy * inno,u32 * config,struct phy_config * phy_cfg,int phy_table_size)1456 int inno_hdmi_update_phy_table(struct inno_hdmi_phy *inno, u32 *config,
1457 struct phy_config *phy_cfg,
1458 int phy_table_size)
1459 {
1460 int i, j;
1461
1462 for (i = 0; i < phy_table_size; i++) {
1463 phy_cfg[i].tmdsclock =
1464 (unsigned long)config[i * 15];
1465
1466 for (j = 0; j < 14; j++)
1467 phy_cfg[i].regs[j] = (u8)config[i * 15 + 1 + j];
1468 }
1469
1470 /*
1471 * The last set of phy cfg is used to indicate whether
1472 * there is no more phy cfg data.
1473 */
1474 phy_cfg[i].tmdsclock = ~0UL;
1475 for (j = 0; j < 14; j++)
1476 phy_cfg[i].regs[j] = 0;
1477
1478 return 0;
1479 }
1480
1481 #define PHY_TAB_LEN 60
1482
inno_hdmi_phy_probe(struct platform_device * pdev)1483 static int inno_hdmi_phy_probe(struct platform_device *pdev)
1484 {
1485 struct device *dev = &pdev->dev;
1486 struct device_node *np = dev->of_node;
1487 struct inno_hdmi_phy *inno;
1488 const struct of_device_id *match;
1489 struct phy_provider *phy_provider;
1490 struct resource *res;
1491 void __iomem *regs;
1492 u32 *phy_config;
1493 int ret, val, phy_table_size;
1494
1495 inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
1496 if (!inno)
1497 return -ENOMEM;
1498
1499 inno->dev = dev;
1500
1501 match = of_match_node(inno_hdmi_phy_of_match, pdev->dev.of_node);
1502 inno->plat_data = (struct inno_hdmi_phy_drv_data *)match->data;
1503 if (!inno->plat_data || !inno->plat_data->ops)
1504 return -EINVAL;
1505
1506 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1507 regs = devm_ioremap_resource(dev, res);
1508 if (IS_ERR(regs))
1509 return PTR_ERR(regs);
1510
1511 inno->sysclk = devm_clk_get(inno->dev, "sysclk");
1512 if (IS_ERR(inno->sysclk)) {
1513 ret = PTR_ERR(inno->sysclk);
1514 dev_err(inno->dev, "Unable to get inno phy sysclk: %d\n", ret);
1515 return ret;
1516 }
1517 ret = clk_prepare_enable(inno->sysclk);
1518 if (ret) {
1519 dev_err(inno->dev, "Cannot enable inno phy sysclk: %d\n", ret);
1520 return ret;
1521 }
1522
1523 inno->regmap = devm_regmap_init_mmio(dev, regs,
1524 &inno_hdmi_phy_regmap_config);
1525 if (IS_ERR(inno->regmap)) {
1526 ret = PTR_ERR(inno->regmap);
1527 dev_err(dev, "failed to init regmap: %d\n", ret);
1528 goto err_regsmap;
1529 }
1530
1531 inno->phy = devm_phy_create(dev, NULL, &inno_hdmi_phy_ops);
1532 if (IS_ERR(inno->phy)) {
1533 dev_err(dev, "failed to create HDMI PHY\n");
1534 ret = PTR_ERR(inno->phy);
1535 goto err_regsmap;
1536 }
1537
1538 if (of_get_property(np, "rockchip,phy-table", &val)) {
1539 if (val % PHY_TAB_LEN || !val) {
1540 dev_err(dev, "Invalid phy cfg table format!\n");
1541 ret = -EINVAL;
1542 goto err_regsmap;
1543 }
1544
1545 phy_config = kmalloc(val, GFP_KERNEL);
1546 if (!phy_config) {
1547 dev_err(dev, "kmalloc phy table failed\n");
1548 ret = -ENOMEM;
1549 goto err_regsmap;
1550 }
1551
1552 phy_table_size = val / PHY_TAB_LEN;
1553 /* Effective phy cfg data and the end of phy cfg table */
1554 inno->phy_cfg = devm_kzalloc(dev, val + PHY_TAB_LEN,
1555 GFP_KERNEL);
1556 if (!inno->phy_cfg) {
1557 kfree(phy_config);
1558 ret = -ENOMEM;
1559 goto err_regsmap;
1560 }
1561 of_property_read_u32_array(np, "rockchip,phy-table",
1562 phy_config, val / sizeof(u32));
1563 ret = inno_hdmi_update_phy_table(inno, phy_config,
1564 inno->phy_cfg,
1565 phy_table_size);
1566 if (ret) {
1567 kfree(phy_config);
1568 goto err_regsmap;
1569 }
1570 kfree(phy_config);
1571 } else {
1572 dev_dbg(dev, "use default hdmi phy table\n");
1573 }
1574
1575 phy_set_drvdata(inno->phy, inno);
1576 phy_set_bus_width(inno->phy, 8);
1577
1578 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1579 if (IS_ERR(phy_provider)) {
1580 dev_err(dev, "failed to register PHY provider\n");
1581 ret = PTR_ERR(phy_provider);
1582 goto err_regsmap;
1583 }
1584
1585 if (inno->plat_data->ops->init)
1586 inno->plat_data->ops->init(inno);
1587
1588 ret = inno_hdmi_phy_clk_register(inno);
1589 if (ret)
1590 goto err_regsmap;
1591
1592 inno->irq = platform_get_irq(pdev, 0);
1593 if (inno->irq > 0) {
1594 ret = devm_request_threaded_irq(inno->dev, inno->irq,
1595 inno_hdmi_phy_hardirq,
1596 inno_hdmi_phy_irq, IRQF_SHARED,
1597 dev_name(inno->dev), inno);
1598 if (ret)
1599 goto err_irq;
1600 }
1601 platform_set_drvdata(pdev, inno);
1602 return 0;
1603
1604 err_irq:
1605 of_clk_del_provider(pdev->dev.of_node);
1606 err_regsmap:
1607 clk_disable_unprepare(inno->sysclk);
1608 return ret;
1609 }
1610
inno_hdmi_phy_remove(struct platform_device * pdev)1611 static int inno_hdmi_phy_remove(struct platform_device *pdev)
1612 {
1613 struct inno_hdmi_phy *inno = platform_get_drvdata(pdev);
1614
1615 of_clk_del_provider(pdev->dev.of_node);
1616 clk_disable_unprepare(inno->sysclk);
1617 return 0;
1618 }
1619
1620 static struct platform_driver inno_hdmi_phy_driver = {
1621 .probe = inno_hdmi_phy_probe,
1622 .remove = inno_hdmi_phy_remove,
1623 .driver = {
1624 .name = "inno-hdmi-phy",
1625 .of_match_table = of_match_ptr(inno_hdmi_phy_of_match),
1626 },
1627 };
1628
1629 module_platform_driver(inno_hdmi_phy_driver);
1630
1631 MODULE_DESCRIPTION("Innosilion HDMI 2.0 Transmitter PHY Driver");
1632 MODULE_LICENSE("GPL v2");
1633