Home
last modified time | relevance | path

Searched refs:con1 (Results 1 – 25 of 47) sorted by relevance

12

/OK3568_Linux_fs/kernel/drivers/iio/adc/
H A Dexynos_adc.c228 u32 con1; in exynos_adc_v1_init_hw() local
234 con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN; in exynos_adc_v1_init_hw()
237 con1 |= ADC_V1_CON_RES; in exynos_adc_v1_init_hw()
238 writel(con1, ADC_V1_CON(info->regs)); in exynos_adc_v1_init_hw()
264 u32 con1; in exynos_adc_v1_start_conv() local
268 con1 = readl(ADC_V1_CON(info->regs)); in exynos_adc_v1_start_conv()
269 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); in exynos_adc_v1_start_conv()
310 u32 con1; in exynos_adc_s3c2416_start_conv() local
313 con1 = readl(ADC_V1_CON(info->regs)); in exynos_adc_s3c2416_start_conv()
314 con1 |= ADC_S3C2416_CON_RES_SEL; in exynos_adc_s3c2416_start_conv()
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/
H A Dpic32_eth.c64 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_mii_init()
71 writel(ETHCON_ON, &ectl_p->con1.set); in pic32_mii_init()
239 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_ctrl_reset()
246 writel(ETHCON_BUFCDEC, &ectl_p->con1.set); in pic32_ctrl_reset()
270 writel(ETHCON_ON, &ectl_p->con1.set); in pic32_ctrl_reset()
297 writel(ETHCON_BUFCDEC, &ectl_p->con1.set); in pic32_rx_desc_init()
319 writel(ETHCON_RXEN, &ectl_p->con1.set); in pic32_rx_desc_init()
356 if (readl(&ectl_p->con1.raw) & ETHCON_ON) in pic32_eth_stop()
363 writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_eth_stop()
374 writel(ETHCON_ON, &ectl_p->con1.clr); in pic32_eth_stop()
[all …]
H A Dgmac_rockchip.c1459 void *con1; in rk3568_set_to_rmii() local
1470 con1 = &grf->mac1_con1; in rk3568_set_to_rmii()
1472 con1 = &grf->mac0_con1; in rk3568_set_to_rmii()
1474 rk_clrsetreg(con1, in rk3568_set_to_rmii()
1482 void *con0, *con1; in rk3568_set_to_rgmii() local
1510 con1 = &grf->mac1_con1; in rk3568_set_to_rgmii()
1513 con1 = &grf->mac0_con1; in rk3568_set_to_rgmii()
1522 rk_clrsetreg(con1, in rk3568_set_to_rgmii()
H A Dpic32_eth.h15 struct pic32_reg_atomic con1; /* 0x00 */ member
/OK3568_Linux_fs/u-boot/drivers/adc/
H A Dexynos-adc.c50 cfg = readl(&regs->con1); in exynos_adc_start_channel()
51 writel(cfg | ADC_V2_CON1_STC_EN, &regs->con1); in exynos_adc_start_channel()
65 cfg = readl(&regs->con1); in exynos_adc_stop()
68 writel(cfg, &regs->con1); in exynos_adc_stop()
88 writel(ADC_V2_CON1_SOFT_RESET, &regs->con1); in exynos_adc_probe()
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/
H A Dclk-regmap-pll.c70 unsigned int con0, con1, con2; in clk_regmap_pll_recalc_rate() local
74 regmap_read(pll->regmap, pll->reg + PLLCON_OFFSET(1), &con1); in clk_regmap_pll_recalc_rate()
80 dsmpd = (con1 & BIT(pll->dsmpd_shift)) >> pll->dsmpd_shift; in clk_regmap_pll_recalc_rate()
81 postdiv2 = (con1 & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in clk_regmap_pll_recalc_rate()
82 refdiv = (con1 & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in clk_regmap_pll_recalc_rate()
317 unsigned int con1; in clk_regmap_pll_is_prepared() local
319 regmap_read(pll->regmap, pll->reg + PLLCON_OFFSET(1), &con1); in clk_regmap_pll_is_prepared()
321 return !(con1 & BIT(pll->pd_shift)); in clk_regmap_pll_is_prepared()
/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk-pll.c439 u32 con0, con1; in samsung_pll45xx_set_rate() local
451 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
453 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { in samsung_pll45xx_set_rate()
471 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
472 con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT); in samsung_pll45xx_set_rate()
473 con1 |= (rate->afc << PLL45XX_AFC_SHIFT); in samsung_pll45xx_set_rate()
488 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
590 u32 con0, con1, lock; in samsung_pll46xx_set_rate() local
602 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
604 if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) { in samsung_pll46xx_set_rate()
[all …]
/OK3568_Linux_fs/kernel/drivers/pwm/
H A Dpwm-mtk-disp.c34 unsigned int con1; member
114 mtk_disp_pwm_update_bits(mdp, mdp->data->con1, in mtk_disp_pwm_config()
256 .con1 = 0xac,
266 .con1 = 0x14,
276 .con1 = 0x1c,
/OK3568_Linux_fs/u-boot/drivers/clk/exynos/
H A Dclk-pll.c20 unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq) in pll145x_get_rate() argument
22 unsigned long pll_con1 = readl(con1); in pll145x_get_rate()
H A Dclk-pll.h9 unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
/OK3568_Linux_fs/kernel/drivers/misc/rk628/
H A Drk628_cru.c64 u32 con0, con1, con2; in rk628_cru_clk_get_rate_pll() local
86 rk628_i2c_read(rk628, offset + CRU_CPLL_CON1, &con1); in rk628_cru_clk_get_rate_pll()
92 dsmpd = (con1 & PLL_DSMPD_MASK) >> PLL_DSMPD_SHIFT; in rk628_cru_clk_get_rate_pll()
93 postdiv2 = (con1 & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rk628_cru_clk_get_rate_pll()
94 refdiv = (con1 & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rk628_cru_clk_get_rate_pll()
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3036.c80 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
83 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
88 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
93 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
96 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
232 con = readl(&pll->con1); in rkclk_pll_get_rate()
H A Dclk_rv1108.c94 rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK, in rkclk_set_pll()
121 uint32_t con0, con1, con3; in rkclk_pll_get_rate() local
130 con1 = readl(&pll->con1); in rkclk_pll_get_rate()
132 postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT; in rkclk_pll_get_rate()
133 postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; in rkclk_pll_get_rate()
134 refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK; in rkclk_pll_get_rate()
/OK3568_Linux_fs/kernel/drivers/media/i2c/rk628/
H A Drk628_cru.c65 u32 con0, con1, con2; in rk628_cru_clk_get_rate_pll() local
87 rk628_i2c_read(rk628, offset + CRU_CPLL_CON1, &con1); in rk628_cru_clk_get_rate_pll()
93 dsmpd = (con1 & PLL_DSMPD_MASK) >> PLL_DSMPD_SHIFT; in rk628_cru_clk_get_rate_pll()
94 postdiv2 = (con1 & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rk628_cru_clk_get_rate_pll()
95 refdiv = (con1 & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rk628_cru_clk_get_rate_pll()
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-pll.c488 u32 con0, u32 con1) in rockchip_rk3036_pll_con_to_rate() argument
497 refdiv = ((con1 >> RK3036_PLLCON1_REFDIV_SHIFT) & in rockchip_rk3036_pll_con_to_rate()
499 postdiv2 = ((con1 >> RK3036_PLLCON1_POSTDIV2_SHIFT) & in rockchip_rk3036_pll_con_to_rate()
1784 u32 con0, u32 con1) in rockchip_pll_con_to_rate() argument
1789 return rockchip_rk3036_pll_con_to_rate(pll, con0, con1); in rockchip_pll_con_to_rate()
1805 u32 value, con0, con1; in rockchip_boost_init() local
1822 !of_property_read_u32(np, "rockchip,boost-low-con1", &con1)) { in rockchip_boost_init()
1823 pr_debug("boost-low-con=0x%x 0x%x\n", con0, con1); in rockchip_boost_init()
1827 HIWORD_UPDATE(con1, BOOST_PLL_CON_MASK, 0)); in rockchip_boost_init()
1829 con1); in rockchip_boost_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Ditd1000.c120 u8 con1 = itd1000_read_reg(state, CON1) & 0xfd; in itd1000_set_lpf_bw() local
128 itd1000_write_reg(state, CON1, con1 | (1 << 1)); in itd1000_set_lpf_bw()
139 itd1000_write_reg(state, CON1, con1 | (0 << 1)); in itd1000_set_lpf_bw()
/OK3568_Linux_fs/buildroot/dl/qt5location/git/src/3rdparty/mapbox-gl-native/deps/boost/1.65.1/include/boost/geometry/index/detail/rtree/rstar/
H A Dredistribute_elements.hpp190 content_type con1 = (std::numeric_limits<content_type>::max)(); in apply() local
194 som1, ovl1, con1, in apply()
209 if ( ovl1 < ovl2 || (ovl1 == ovl2 && con1 <= con2) ) in apply()
214 smallest_content = con1; in apply()
/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3308.c81 rk_clrsetreg(&priv->cru->pll[pll_type].con1, PLLPD0_MASK, in pll_set()
83 rk_clrsetreg(&priv->cru->pll[pll_type].con1, in pll_set()
91 rk_clrsetreg(&priv->cru->pll[pll_type].con1, in pll_set()
98 rk_clrsetreg(&priv->cru->pll[pll_type].con1, PLLPD0_MASK, in pll_set()
102 while (!(readl(&priv->cru->pll[pll_type].con1) & in pll_set()
588 writel(CG_EXIT_TH << CG_EXIT_TH_SHIFT, &priv->standby->con1); in enable_ddr_standby()
/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/include/mach/
H A Dadc.h59 unsigned int con1; member
/OK3568_Linux_fs/kernel/drivers/i2c/busses/
H A Di2c-rk3x.c294 unsigned int len, con1 = 0; in rk3x_i2c_auto_stop() local
300 con1 = REG_CON1_NACK_AUTO_STOP | REG_CON1_AUTO_STOP; in rk3x_i2c_auto_stop()
312 con1 |= REG_CON1_TRANSFER_AUTO_STOP | REG_CON1_AUTO_STOP; in rk3x_i2c_auto_stop()
313 i2c_writel(i2c, con1, REG_CON1); in rk3x_i2c_auto_stop()
314 if (con1 & REG_CON1_NACK_AUTO_STOP) in rk3x_i2c_auto_stop()
322 i2c_writel(i2c, con1, REG_CON1); in rk3x_i2c_auto_stop()
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c336 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkdclk_init()
342 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkdclk_init()
347 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkdclk_init()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3188.h42 u32 con1; member
H A Dcru_rk3066.h42 u32 con1; member
H A Dsdram_rk3308.h22 u32 con1; member
H A Dcru_rk3368.h32 unsigned int con1; member

12