1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __MICROCHIP_PIC32_ETH_H_ 9*4882a593Smuzhiyun #define __MICROCHIP_PIC32_ETH_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <mach/pic32.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Ethernet */ 14*4882a593Smuzhiyun struct pic32_ectl_regs { 15*4882a593Smuzhiyun struct pic32_reg_atomic con1; /* 0x00 */ 16*4882a593Smuzhiyun struct pic32_reg_atomic con2; /* 0x10 */ 17*4882a593Smuzhiyun struct pic32_reg_atomic txst; /* 0x20 */ 18*4882a593Smuzhiyun struct pic32_reg_atomic rxst; /* 0x30 */ 19*4882a593Smuzhiyun struct pic32_reg_atomic ht0; /* 0x40 */ 20*4882a593Smuzhiyun struct pic32_reg_atomic ht1; /* 0x50 */ 21*4882a593Smuzhiyun struct pic32_reg_atomic pmm0; /* 0x60 */ 22*4882a593Smuzhiyun struct pic32_reg_atomic pmm1; /* 0x70 */ 23*4882a593Smuzhiyun struct pic32_reg_atomic pmcs; /* 0x80 */ 24*4882a593Smuzhiyun struct pic32_reg_atomic pmo; /* 0x90 */ 25*4882a593Smuzhiyun struct pic32_reg_atomic rxfc; /* 0xa0 */ 26*4882a593Smuzhiyun struct pic32_reg_atomic rxwm; /* 0xb0 */ 27*4882a593Smuzhiyun struct pic32_reg_atomic ien; /* 0xc0 */ 28*4882a593Smuzhiyun struct pic32_reg_atomic irq; /* 0xd0 */ 29*4882a593Smuzhiyun struct pic32_reg_atomic stat; /* 0xe0 */ 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun struct pic32_mii_regs { 33*4882a593Smuzhiyun struct pic32_reg_atomic mcfg; /* 0x280 */ 34*4882a593Smuzhiyun struct pic32_reg_atomic mcmd; /* 0x290 */ 35*4882a593Smuzhiyun struct pic32_reg_atomic madr; /* 0x2a0 */ 36*4882a593Smuzhiyun struct pic32_reg_atomic mwtd; /* 0x2b0 */ 37*4882a593Smuzhiyun struct pic32_reg_atomic mrdd; /* 0x2c0 */ 38*4882a593Smuzhiyun struct pic32_reg_atomic mind; /* 0x2d0 */ 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct pic32_emac_regs { 42*4882a593Smuzhiyun struct pic32_reg_atomic cfg1; /* 0x200*/ 43*4882a593Smuzhiyun struct pic32_reg_atomic cfg2; /* 0x210*/ 44*4882a593Smuzhiyun struct pic32_reg_atomic ipgt; /* 0x220*/ 45*4882a593Smuzhiyun struct pic32_reg_atomic ipgr; /* 0x230*/ 46*4882a593Smuzhiyun struct pic32_reg_atomic clrt; /* 0x240*/ 47*4882a593Smuzhiyun struct pic32_reg_atomic maxf; /* 0x250*/ 48*4882a593Smuzhiyun struct pic32_reg_atomic supp; /* 0x260*/ 49*4882a593Smuzhiyun struct pic32_reg_atomic test; /* 0x270*/ 50*4882a593Smuzhiyun struct pic32_mii_regs mii; /* 0x280 - 0x2d0 */ 51*4882a593Smuzhiyun struct pic32_reg_atomic res1; /* 0x2e0 */ 52*4882a593Smuzhiyun struct pic32_reg_atomic res2; /* 0x2f0 */ 53*4882a593Smuzhiyun struct pic32_reg_atomic sa0; /* 0x300 */ 54*4882a593Smuzhiyun struct pic32_reg_atomic sa1; /* 0x310 */ 55*4882a593Smuzhiyun struct pic32_reg_atomic sa2; /* 0x320 */ 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* ETHCON1 Reg field */ 59*4882a593Smuzhiyun #define ETHCON_BUFCDEC BIT(0) 60*4882a593Smuzhiyun #define ETHCON_RXEN BIT(8) 61*4882a593Smuzhiyun #define ETHCON_TXRTS BIT(9) 62*4882a593Smuzhiyun #define ETHCON_ON BIT(15) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* ETHCON2 Reg field */ 65*4882a593Smuzhiyun #define ETHCON_RXBUFSZ 0x7f 66*4882a593Smuzhiyun #define ETHCON_RXBUFSZ_SHFT 0x4 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* ETHSTAT Reg field */ 69*4882a593Smuzhiyun #define ETHSTAT_BUSY BIT(7) 70*4882a593Smuzhiyun #define ETHSTAT_BUFCNT 0x00ff0000 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* ETHRXFC Register fields */ 73*4882a593Smuzhiyun #define ETHRXFC_BCEN BIT(0) 74*4882a593Smuzhiyun #define ETHRXFC_MCEN BIT(1) 75*4882a593Smuzhiyun #define ETHRXFC_UCEN BIT(3) 76*4882a593Smuzhiyun #define ETHRXFC_RUNTEN BIT(4) 77*4882a593Smuzhiyun #define ETHRXFC_CRCOKEN BIT(5) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* EMAC1CFG1 register offset */ 80*4882a593Smuzhiyun #define PIC32_EMAC1CFG1 0x0200 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* EMAC1CFG1 register fields */ 83*4882a593Smuzhiyun #define EMAC_RXENABLE BIT(0) 84*4882a593Smuzhiyun #define EMAC_RXPAUSE BIT(2) 85*4882a593Smuzhiyun #define EMAC_TXPAUSE BIT(3) 86*4882a593Smuzhiyun #define EMAC_SOFTRESET BIT(15) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* EMAC1CFG2 register fields */ 89*4882a593Smuzhiyun #define EMAC_FULLDUP BIT(0) 90*4882a593Smuzhiyun #define EMAC_LENGTHCK BIT(1) 91*4882a593Smuzhiyun #define EMAC_CRCENABLE BIT(4) 92*4882a593Smuzhiyun #define EMAC_PADENABLE BIT(5) 93*4882a593Smuzhiyun #define EMAC_AUTOPAD BIT(7) 94*4882a593Smuzhiyun #define EMAC_EXCESS BIT(14) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* EMAC1IPGT register magic */ 97*4882a593Smuzhiyun #define FULLDUP_GAP_TIME 0x15 98*4882a593Smuzhiyun #define HALFDUP_GAP_TIME 0x12 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* EMAC1SUPP register fields */ 101*4882a593Smuzhiyun #define EMAC_RMII_SPD100 BIT(8) 102*4882a593Smuzhiyun #define EMAC_RMII_RESET BIT(11) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* MII Management Configuration Register */ 105*4882a593Smuzhiyun #define MIIMCFG_RSTMGMT BIT(15) 106*4882a593Smuzhiyun #define MIIMCFG_CLKSEL_DIV40 0x0020 /* 100Mhz / 40 */ 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* MII Management Command Register */ 109*4882a593Smuzhiyun #define MIIMCMD_READ BIT(0) 110*4882a593Smuzhiyun #define MIIMCMD_SCAN BIT(1) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* MII Management Address Register */ 113*4882a593Smuzhiyun #define MIIMADD_REGADDR 0x1f 114*4882a593Smuzhiyun #define MIIMADD_REGADDR_SHIFT 0 115*4882a593Smuzhiyun #define MIIMADD_PHYADDR_SHIFT 8 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* MII Management Indicator Register */ 118*4882a593Smuzhiyun #define MIIMIND_BUSY BIT(0) 119*4882a593Smuzhiyun #define MIIMIND_NOTVALID BIT(2) 120*4882a593Smuzhiyun #define MIIMIND_LINKFAIL BIT(3) 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* Packet Descriptor */ 123*4882a593Smuzhiyun /* Received Packet Status */ 124*4882a593Smuzhiyun #define _RSV1_PKT_CSUM 0xffff 125*4882a593Smuzhiyun #define _RSV2_CRC_ERR BIT(20) 126*4882a593Smuzhiyun #define _RSV2_LEN_ERR BIT(21) 127*4882a593Smuzhiyun #define _RSV2_RX_OK BIT(23) 128*4882a593Smuzhiyun #define _RSV2_RX_COUNT 0xffff 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define RSV_RX_CSUM(__rsv1) ((__rsv1) & _RSV1_PKT_CSUM) 131*4882a593Smuzhiyun #define RSV_RX_COUNT(__rsv2) ((__rsv2) & _RSV2_RX_COUNT) 132*4882a593Smuzhiyun #define RSV_RX_OK(__rsv2) ((__rsv2) & _RSV2_RX_OK) 133*4882a593Smuzhiyun #define RSV_CRC_ERR(__rsv2) ((__rsv2) & _RSV2_CRC_ERR) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* Ethernet Hardware Descriptor Header bits */ 136*4882a593Smuzhiyun #define EDH_EOWN BIT(7) 137*4882a593Smuzhiyun #define EDH_NPV BIT(8) 138*4882a593Smuzhiyun #define EDH_STICKY BIT(9) 139*4882a593Smuzhiyun #define _EDH_BCOUNT 0x07ff0000 140*4882a593Smuzhiyun #define EDH_EOP BIT(30) 141*4882a593Smuzhiyun #define EDH_SOP BIT(31) 142*4882a593Smuzhiyun #define EDH_BCOUNT_SHIFT 16 143*4882a593Smuzhiyun #define EDH_BCOUNT(len) ((len) << EDH_BCOUNT_SHIFT) 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* Ethernet Hardware Descriptors 146*4882a593Smuzhiyun * ref: PIC32 Family Reference Manual Table 35-7 147*4882a593Smuzhiyun * This structure represents the layout of the DMA 148*4882a593Smuzhiyun * memory shared between the CPU and the Ethernet 149*4882a593Smuzhiyun * controller. 150*4882a593Smuzhiyun */ 151*4882a593Smuzhiyun /* TX/RX DMA descriptor */ 152*4882a593Smuzhiyun struct eth_dma_desc { 153*4882a593Smuzhiyun u32 hdr; /* header */ 154*4882a593Smuzhiyun u32 data_buff; /* data buffer address */ 155*4882a593Smuzhiyun u32 stat1; /* transmit/receive packet status */ 156*4882a593Smuzhiyun u32 stat2; /* transmit/receive packet status */ 157*4882a593Smuzhiyun u32 next_ed; /* next descriptor */ 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun #define PIC32_MDIO_NAME "PIC32_EMAC" 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun int pic32_mdio_init(const char *name, ulong ioaddr); 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun #endif /* __MICROCHIP_PIC32_ETH_H_*/ 165