xref: /OK3568_Linux_fs/u-boot/drivers/clk/exynos/clk-pll.c (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Exynos PLL helper functions for clock drivers.
3*4882a593Smuzhiyun  * Copyright (C) 2016 Samsung Electronics
4*4882a593Smuzhiyun  * Thomas Abraham <thomas.ab@samsung.com>
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <div64.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define PLL145X_MDIV_SHIFT	16
14*4882a593Smuzhiyun #define PLL145X_MDIV_MASK	0x3ff
15*4882a593Smuzhiyun #define PLL145X_PDIV_SHIFT	8
16*4882a593Smuzhiyun #define PLL145X_PDIV_MASK	0x3f
17*4882a593Smuzhiyun #define PLL145X_SDIV_SHIFT	0
18*4882a593Smuzhiyun #define PLL145X_SDIV_MASK	0x7
19*4882a593Smuzhiyun 
pll145x_get_rate(unsigned int * con1,unsigned long fin_freq)20*4882a593Smuzhiyun unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun 	unsigned long pll_con1 = readl(con1);
23*4882a593Smuzhiyun 	unsigned long mdiv, sdiv, pdiv;
24*4882a593Smuzhiyun 	uint64_t fvco = fin_freq;
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun 	mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
27*4882a593Smuzhiyun 	pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
28*4882a593Smuzhiyun 	sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 	fvco *= mdiv;
31*4882a593Smuzhiyun 	do_div(fvco, (pdiv << sdiv));
32*4882a593Smuzhiyun 	return (unsigned long)fvco;
33*4882a593Smuzhiyun }
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