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Searched refs:clrbits_le32 (Results 1 – 25 of 210) sorted by relevance

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/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Dsdram_phy_px30.c20 clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3); in sdram_phy_dll_bypass_set()
24 clrbits_le32(PHY_REG(phy_base, j + 0x1), 1 << 3); in sdram_phy_dll_bypass_set()
31 clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); in sdram_phy_dll_bypass_set()
88 clrbits_le32(PHY_REG(phy_base, 0), 0x3 << 2); in phy_soft_reset()
104 clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3); in phy_dram_set_bw()
105 clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3); in phy_dram_set_bw()
108 clrbits_le32(PHY_REG(phy_base, 0x36), 1 << 3); in phy_dram_set_bw()
109 clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3); in phy_dram_set_bw()
110 clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3); in phy_dram_set_bw()
145 clrbits_le32(PHY_REG(phy_base, 2), 0x30); in phy_data_training()
[all …]
H A Dsdram_rk3188.c131 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
133 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
154 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
164 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
165 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); in phy_dll_bypass_set()
167 clrbits_le32(&publ->datx8[i].dxdllcr, in phy_dll_bypass_set()
171 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
285 clrbits_le32(&publ->pgcr, 0x1f); in phy_cfg()
297 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); in phy_cfg()
391 clrbits_le32(&publ->datx8[2].dxgcr, 1); in set_bandwidth_ratio()
[all …]
H A Dsdram_rk3288.c130 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
132 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
153 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
163 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
164 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); in phy_dll_bypass_set()
166 clrbits_le32(&publ->datx8[i].dxdllcr, in phy_dll_bypass_set()
170 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
343 clrbits_le32(&publ->pgcr, 0x1f); in phy_cfg()
355 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); in phy_cfg()
449 clrbits_le32(&publ->datx8[2].dxgcr, 1); in set_bandwidth_ratio()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/
H A Dda850_lowlevel.c41 clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK); in da850_pll_init()
47 clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC); in da850_pll_init()
49 clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC); in da850_pll_init()
52 clrbits_le32(&reg->pllctl, PLLCTL_PLLEN); in da850_pll_init()
67 clrbits_le32(&reg->pllctl, PLLCTL_PLLRST); in da850_pll_init()
77 clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN); in da850_pll_init()
80 clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS); in da850_pll_init()
173 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); in da850_ddr_setup()
174 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); in da850_ddr_setup()
176 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); in da850_ddr_setup()
[all …]
H A Ddm365_lowlevel.c31 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN); in dm365_pll1_init()
33 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9); in dm365_pll1_init()
41 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC); in dm365_pll1_init()
44 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); in dm365_pll1_init()
54 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
108 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN); in dm365_pll2_init()
115 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9); in dm365_pll2_init()
123 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC); in dm365_pll2_init()
126 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN); in dm365_pll2_init()
136 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST); in dm365_pll2_init()
[all …]
/OK3568_Linux_fs/u-boot/drivers/fpga/
H A Dsocfpga_arria10.c53 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_set_cfgwdth()
133 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_set_cd_ratio()
227 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_reset()
289 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_init()
292 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_program_init()
299 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_init()
309 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_init()
311 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_init()
327 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_init()
394 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_program_poll_usermode()
H A Dsocfpga_gen5.c62 clrbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_program_init()
78 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); in fpgamgr_program_init()
99 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); in fpgamgr_program_init()
151 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); in fpgamgr_program_poll_cd()
199 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); in fpgamgr_program_poll_usermode()
/OK3568_Linux_fs/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dspl_power_init.c319 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); in mxs_src_power_init()
378 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); in mxs_enable_4p2_dcdc_input()
382 clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP); in mxs_enable_4p2_dcdc_input()
398 clrbits_le32(&power_regs->hw_power_5vctrl, in mxs_enable_4p2_dcdc_input()
408 clrbits_le32(&power_regs->hw_power_5vctrl, in mxs_enable_4p2_dcdc_input()
427 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO); in mxs_enable_4p2_dcdc_input()
450 clrbits_le32(&power_regs->hw_power_ctrl, in mxs_enable_4p2_dcdc_input()
477 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK); in mxs_power_init_4p2_regulator()
498 clrbits_le32(&power_regs->hw_power_dcdc4p2, in mxs_power_init_4p2_regulator()
549 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK); in mxs_power_init_4p2_regulator()
[all …]
H A Dspl_mem_init.c260 clrbits_le32(&power_regs->hw_power_vddmemctrl, in mx23_mem_setup_vddmem()
285 clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8)); in mx23_mem_init()
292 clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17); in mx23_mem_init()
327 clrbits_le32(MXS_DRAM_BASE + 0x40, 1); in mx28_mem_init()
332 clrbits_le32(MXS_DRAM_BASE + 0x44, 1); in mx28_mem_init()
/OK3568_Linux_fs/u-boot/drivers/i2c/
H A Dzynq_i2c.c167 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_probe()
200 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_read()
203 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); in zynq_i2c_read()
211 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_read()
229 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_read()
238 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_read()
259 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); in zynq_i2c_write()
268 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_write()
279 clrbits_le32(&zynq_i2c->control, in zynq_i2c_write()
287 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_write()
/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Dusb_phy.c131 clrbits_le32(dest, 0xff << 8); in usb_phy_write()
134 clrbits_le32(dest, usbc_bit); in usb_phy_write()
139 clrbits_le32(dest, 1 << 7); in usb_phy_write()
143 clrbits_le32(dest, usbc_bit); in usb_phy_write()
154 clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); in sunxi_usb_phy_config()
156 clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02); in sunxi_usb_phy_config()
209 clrbits_le32(addr, bits); in sunxi_usb_phy_passby()
243 clrbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, in sunxi_usb_phy_init()
268 clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask); in sunxi_usb_phy_exit()
385 clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); in sunxi_usb_phy_remove()
H A Ddram_sun4i.c76 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
80 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
123 clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF); in mctl_itm_enable()
143 clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE); in mctl_enable_dll0()
181 clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET | in mctl_enable_dllx()
296 clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE); in mctl_setup_dram_clock()
299 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); in mctl_setup_dram_clock()
339 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); in mctl_setup_dram_clock()
341 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); in mctl_setup_dram_clock()
391 clrbits_le32(&dram->csr, DRAM_CSR_FAILED); in dramc_scan_readpipe()
[all …]
H A Ddram_sunxi_dw.c34 clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26); in mctl_set_bit_delays()
372 clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); in mctl_sys_init()
373 clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); in mctl_sys_init()
374 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
375 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
376 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init()
378 clrbits_le32(&ccm->pll11_cfg, CCM_PLL11_CTRL_EN); in mctl_sys_init()
381 clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); in mctl_sys_init()
434 clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f); in mctl_channel_init()
470 clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12)); in mctl_channel_init()
[all …]
H A Ddram_sun8i_a83t.c278 clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0 | 0x1 << 30); in mctl_channel_init()
321 clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6)); in mctl_channel_init()
322 clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7)); in mctl_channel_init()
396 clrbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE); in mctl_sys_init()
397 clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); in mctl_sys_init()
398 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
399 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
400 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init()
402 clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31); in mctl_sys_init()
/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/
H A Dpower.c51 clrbits_le32(&power->usbhost_phy_control, in exynos5_set_usbhost_phy_ctrl()
71 clrbits_le32(&power->usbhost_phy_control, in exynos4412_set_usbhost_phy_ctrl()
73 clrbits_le32(&power->hsic1_phy_control, in exynos4412_set_usbhost_phy_ctrl()
75 clrbits_le32(&power->hsic2_phy_control, in exynos4412_set_usbhost_phy_ctrl()
100 clrbits_le32(&power->usbdrd_phy_control, in exynos5_set_usbdrd_phy_ctrl()
118 clrbits_le32(&power->usbdev_phy_control, in exynos5420_set_usbdev_phy_ctrl()
120 clrbits_le32(&power->usbdev1_phy_control, in exynos5420_set_usbdev_phy_ctrl()
H A Dspl_boot.c75 clrbits_le32(&regs->ch_cfg, SPI_CH_RST); in spi_rx_tx()
124 clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ in exynos_spi_copy()
127 clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); in exynos_spi_copy()
135 clrbits_le32(&regs->ch_cfg, SPI_CH_RST); in exynos_spi_copy()
139 clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ in exynos_spi_copy()
165 clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD | in exynos_spi_copy()
174 clrbits_le32(&regs->ch_cfg, SPI_CH_RST); in exynos_spi_copy()
175 clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); in exynos_spi_copy()
/OK3568_Linux_fs/u-boot/drivers/usb/host/
H A Dehci-exynos.c89 clrbits_le32(&usb->usbphyctrl0, in exynos5_setup_usb_phy()
106 clrbits_le32(&usb->usbphyctrl0, in exynos5_setup_usb_phy()
115 clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl); in exynos5_setup_usb_phy()
116 clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl); in exynos5_setup_usb_phy()
129 clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST | in exynos5_setup_usb_phy()
132 clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST | in exynos5_setup_usb_phy()
149 clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 | in exynos4412_setup_usb_phy()
155 clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST)); in exynos4412_setup_usb_phy()
H A Dehci-tegra.c323 clrbits_le32(&usbctlr->port_sc1, STS1); in init_phy_mux()
327 clrbits_le32(&usbctlr->port_sc1, STS); in init_phy_mux()
342 clrbits_le32(&usbctlr->hostpc1_devlc, STS); in init_phy_mux()
364 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); in init_utmi_usb_controller()
434 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, in init_utmi_usb_controller()
468 clrbits_le32(&usbctlr->utmip_misc_cfg0, in init_utmi_usb_controller()
497 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); in init_utmi_usb_controller()
530 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, in init_utmi_usb_controller()
533 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, in init_utmi_usb_controller()
536 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, in init_utmi_usb_controller()
[all …]
/OK3568_Linux_fs/u-boot/board/kmc/kzm9g/
H A Dkzm9g.c152 clrbits_le32(&cpg->smstpcr3, (1 << 15)); in s_init()
153 clrbits_le32(&cpg_srcr->srcr3, (1 << 15)); in s_init()
154 clrbits_le32(&cpg->smstpcr2, (1 << 18)); in s_init()
155 clrbits_le32(&cpg_srcr->srcr2, (1 << 18)); in s_init()
167 clrbits_le32(&cpg->smstpcr0, (1 << 1)); in s_init()
169 clrbits_le32(&cpg_srcr->srcr0, (1 << 1)); in s_init()
235 clrbits_le32(&cpg->pllecr, (1 << 3)); in s_init()
273 clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); in board_early_init_f()
274 clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); in board_early_init_f()
275 clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); in board_early_init_f()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/
H A Dfreeze_controller.c51 clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); in sys_mgr_frzctrl_freeze_req()
61 clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); in sys_mgr_frzctrl_freeze_req()
76 clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); in sys_mgr_frzctrl_freeze_req()
156 clrbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
199 clrbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
H A Dreset_manager_arria10.c139 clrbits_le32(&reset_manager_base->brgmodrst, in socfpga_reset_deassert_noc_ddr_scheduler()
188 clrbits_le32(&reset_manager_base->per0modrst, emacmask); in socfpga_emac_manage_reset()
189 clrbits_le32(&reset_manager_base->per0modrst, eccmask); in socfpga_emac_manage_reset()
222 clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr); in socfpga_reset_deassert_bridges_handoff()
252 clrbits_le32(&reset_manager_base->per1modrst, in socfpga_reset_deassert_osc1wd0()
288 clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); in socfpga_per_reset()
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3066/
H A Dsdram_rk3066.c131 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
133 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
154 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
164 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
165 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); in phy_dll_bypass_set()
167 clrbits_le32(&publ->datx8[i].dxdllcr, in phy_dll_bypass_set()
171 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
274 clrbits_le32(&publ->pgcr, 0x1f); in phy_cfg()
286 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); in phy_cfg()
379 clrbits_le32(&publ->datx8[2].dxgcr, 1); in set_bandwidth_ratio()
[all …]
/OK3568_Linux_fs/u-boot/board/solidrun/clearfog/
H A Dclearfog.c133 clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); in board_init()
134 clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9)); in board_init()
136 clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19)); in board_init()
137 clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19)); in board_init()
/OK3568_Linux_fs/u-boot/board/amlogic/odroid-c2/
H A Dodroid-c2.c39 clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK); in misc_init_r()
42 clrbits_le32(GXBB_GPIO_EN(3), BIT(14)); in misc_init_r()
43 clrbits_le32(GXBB_GPIO_OUT(3), BIT(14)); in misc_init_r()
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/sunxi/
H A Dpsci.c111 clrbits_le32(pwroff, BIT(cpu)); in sunxi_power_switch()
186 clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu)); in sunxi_cpu_power_off()
262 clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu)); in psci_cpu_on()
265 clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu)); in psci_cpu_on()
297 clrbits_le32(GICD_BASE + GICD_IGROUPRn, BIT(15)); in psci_arch_init()

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