Lines Matching refs:clrbits_le32

41 		clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);  in da850_pll_init()
47 	clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);  in da850_pll_init()
49 	clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);  in da850_pll_init()
52 	clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);  in da850_pll_init()
67 	clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);  in da850_pll_init()
77 	clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);  in da850_pll_init()
80 	clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);  in da850_pll_init()
173 		clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);  in da850_ddr_setup()
174 		clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);  in da850_ddr_setup()
176 		clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);  in da850_ddr_setup()
192 		clrbits_le32(&davinci_syscfg1_regs->ddr_slew,  in da850_ddr_setup()
247 	clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,  in da850_ddr_setup()