Lines Matching refs:clrbits_le32
76 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
80 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
123 clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF); in mctl_itm_enable()
143 clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE); in mctl_enable_dll0()
181 clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET | in mctl_enable_dllx()
296 clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE); in mctl_setup_dram_clock()
299 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); in mctl_setup_dram_clock()
339 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); in mctl_setup_dram_clock()
341 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); in mctl_setup_dram_clock()
391 clrbits_le32(&dram->csr, DRAM_CSR_FAILED); in dramc_scan_readpipe()
413 clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); in dramc_clock_output_en()
420 clrbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT); in dramc_clock_output_en()
540 clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL); in mctl_set_impedance()
556 clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL); in mctl_set_impedance()
681 clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE); in dramc_init_helper()