1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/arch/gxbb.h>
11*4882a593Smuzhiyun #include <asm/arch/sm.h>
12*4882a593Smuzhiyun #include <phy.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define EFUSE_SN_OFFSET 20
15*4882a593Smuzhiyun #define EFUSE_SN_SIZE 16
16*4882a593Smuzhiyun #define EFUSE_MAC_OFFSET 52
17*4882a593Smuzhiyun #define EFUSE_MAC_SIZE 6
18*4882a593Smuzhiyun
board_init(void)19*4882a593Smuzhiyun int board_init(void)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun return 0;
22*4882a593Smuzhiyun }
23*4882a593Smuzhiyun
misc_init_r(void)24*4882a593Smuzhiyun int misc_init_r(void)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun u8 mac_addr[EFUSE_MAC_SIZE];
27*4882a593Smuzhiyun char serial[EFUSE_SN_SIZE];
28*4882a593Smuzhiyun ssize_t len;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* Set RGMII mode */
31*4882a593Smuzhiyun setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
32*4882a593Smuzhiyun GXBB_ETH_REG_0_TX_PHASE(1) |
33*4882a593Smuzhiyun GXBB_ETH_REG_0_TX_RATIO(4) |
34*4882a593Smuzhiyun GXBB_ETH_REG_0_PHY_CLK_EN |
35*4882a593Smuzhiyun GXBB_ETH_REG_0_CLK_EN);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Enable power and clock gate */
38*4882a593Smuzhiyun setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
39*4882a593Smuzhiyun clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* Reset PHY on GPIOZ_14 */
42*4882a593Smuzhiyun clrbits_le32(GXBB_GPIO_EN(3), BIT(14));
43*4882a593Smuzhiyun clrbits_le32(GXBB_GPIO_OUT(3), BIT(14));
44*4882a593Smuzhiyun mdelay(10);
45*4882a593Smuzhiyun setbits_le32(GXBB_GPIO_OUT(3), BIT(14));
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
48*4882a593Smuzhiyun len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
49*4882a593Smuzhiyun mac_addr, EFUSE_MAC_SIZE);
50*4882a593Smuzhiyun if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
51*4882a593Smuzhiyun eth_env_set_enetaddr("ethaddr", mac_addr);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun if (!env_get("serial#")) {
55*4882a593Smuzhiyun len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
56*4882a593Smuzhiyun EFUSE_SN_SIZE);
57*4882a593Smuzhiyun if (len == EFUSE_SN_SIZE)
58*4882a593Smuzhiyun env_set("serial#", serial);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return 0;
62*4882a593Smuzhiyun }
63