| /OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/ |
| H A D | Kconfig | 6 bool "NAND ECC Smart Media byte order"
14 tristate "Raw/Parallel NAND Device Support"
20 NAND flash devices. For further information see
32 ECC codes. They are used with NAND devices requiring more than 1 bit
35 comment "Raw/parallel NAND flash controllers"
41 tristate "Denali NAND controller on Intel Moorestown"
45 Enable the driver for NAND flash on Intel Moorestown, using the
46 Denali NAND controller core.
49 tristate "Denali NAND controller as a DT device"
53 Enable the driver for NAND flash on platforms using a Denali NAND
[all …]
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| /OK3568_Linux_fs/u-boot/drivers/mtd/nand/raw/ |
| H A D | Kconfig | 2 menuconfig NAND config
3 bool "Raw NAND Device Support"
4 if NAND
10 NAND initialization process.
19 bool "Support Atmel NAND controller"
22 Enable this driver for NAND flash platforms using an Atmel NAND
64 bool "Support Broadcom NAND controller"
67 Enable the driver for NAND flash on platforms using a Broadcom NAND
71 bool "Support Broadcom NAND controller on bcm6838"
77 bool "Support Broadcom NAND controller on bcm6858"
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra30/ |
| H A D | pinmux.c | 138 PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT),
139 PIN(GMI_IORDY_PI5, RSVD1, NAND, GMI, RSVD4),
140 PIN(GMI_WAIT_PI7, RSVD1, NAND, GMI, RSVD4),
141 PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, RSVD4),
142 PIN(GMI_CLK_PK1, RSVD1, NAND, GMI, RSVD4),
143 PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, DTV),
144 PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, DTV),
145 PIN(GMI_CS2_N_PK3, RSVD1, NAND, GMI, RSVD4),
146 PIN(GMI_CS3_N_PK4, RSVD1, NAND, GMI, GMI_ALT),
147 PIN(GMI_CS4_N_PK2, RSVD1, NAND, GMI, RSVD4),
[all …]
|
| /OK3568_Linux_fs/u-boot/doc/ |
| H A D | README.nand-boot-ppc440 | 2 NAND boot on PPC440 platforms
5 This document describes the U-Boot NAND boot feature as it
8 The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH,
9 completely without NOR FLASH. This can be done by using the NAND
10 boot feature of the 440 NAND flash controller (NDFC).
16 Will load first 4k from NAND (SPL) into cache and execute it from there.
20 Will load special U-Boot version (NUB) from NAND and execute it. This SPL
22 controller and the NAND controller so that the special U-Boot image can be
23 loaded from NAND to SDRAM.
26 c) NUB (NAND U-Boot)
[all …]
|
| H A D | README.nand | 1 NAND FLASH commands and notes
16 Print information about the current NAND device.
41 Print information about all of the NAND devices found.
44 Read `size' bytes from `ofs' in NAND flash to `addr'. Blocks that
50 `ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
55 Write `size' bytes from `addr' to `ofs' in NAND flash. Blocks that
67 the NAND flash in a manner identical to the 'nand write' command
70 NAND flash. This behaviour is required when flashing UBI images
77 corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
83 Read or write one or more pages at "ofs" in NAND flash, from or to
[all …]
|
| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra114/ |
| H A D | pinmux.c | 141 PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT),
143 PIN(GMI_WAIT_PI7, SPI4, NAND, GMI, DTV),
144 PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, TRACE),
145 PIN(GMI_CLK_PK1, SDMMC2, NAND, GMI, TRACE),
146 PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, USB),
147 PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, SOC),
148 PIN(GMI_CS2_N_PK3, SDMMC2, NAND, GMI, TRACE),
149 PIN(GMI_CS3_N_PK4, SDMMC2, NAND, GMI, GMI_ALT),
150 PIN(GMI_CS4_N_PK2, USB, NAND, GMI, TRACE),
151 PIN(GMI_CS6_N_PI3, NAND, NAND_ALT, GMI, SPI4),
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/ |
| H A D | brcm,brcmnand.txt | 1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
19 the core NAND controller, of the following form:
35 - reg : the register start and length for NAND register region.
37 (optional) NAND flash cache range (if at non-standard offset)
41 - interrupts : The NAND CTLRDY interrupt, (if Flash DMA is available)
45 May be "nand", if the SoC has the individual NAND
52 - clock : reference to the clock for the NAND controller
59 -- Additional SoC-specific NAND controller properties --
61 The NAND controller is integrated differently on the variety of SoCs on which it
[all …]
|
| H A D | mtk-nand.txt | 1 MTK SoCs NAND FLASH controller (NFC) DT binding
3 This file documents the device tree bindings for MTK SoCs NAND controllers.
10 1) NFC NAND Controller Interface (NFI):
13 The first part of NFC is NAND Controller Interface (NFI) HW.
24 - #address-cells: NAND chip index, should be 1.
42 - children nodes: NAND chips.
48 - nand-on-flash-bbt: Store BBT on NAND Flash.
49 - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
74 According to MTK NAND controller design,
76 that MTK NAND controller supports.
[all …]
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| H A D | qcom_nandc.txt | 1 * Qualcomm NAND controller
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
9 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
20 NAND. Refer to dma.txt and qcom_adm.txt for more details
23 number specified for the NAND controller on the given
26 number specified for the NAND controller on the given
31 and the channel number to be used for NAND. Refer to
37 * NAND chip-select
40 chip-selects which (may) contain NAND flash chips. Their properties are as
|
| H A D | atmel-nand.txt | 1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
30 * NAND device/chip bindings:
33 - reg: describes the CS lines assigned to the NAND device. If the NAND device
36 1st entry: the CS line this NAND chip is connected to
42 - rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
49 Documentation/devicetree/bindings/mtd/{common,nand}.txt also apply to the NAND
[all …]
|
| H A D | oxnas-nand.txt | 1 * Oxford Semiconductor OXNAS NAND Controller
3 Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings.
7 - reg: Base address and length for NAND mapped memory.
10 - clocks: phandle to the NAND gate clock if needed.
11 - resets: phandle to the NAND reset control if needed.
|
| H A D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller
18 Individual NAND chips are children of the NAND controller node. Currently
19 only one NAND chip supported.
25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
41 Optional child node of NAND chip nodes:
|
| H A D | fsmc-nand.txt | 2 NAND Interface
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
27 NAND flash in response to SMWAITn. Zero means 1 cycle,
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
47 0xd2000000 0x0010 /* NAND Base DATA */
48 0xd2020000 0x0010 /* NAND Base ADDR */
49 0xd2010000 0x0010>; /* NAND Base CMD */
|
| H A D | marvell-nand.txt | 1 Marvell NAND Flash Controller (NFC)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
16 - interrupts: shall define the NAND controller interrupt.
17 - clocks: shall reference the NAND controller clocks, the second one is
22 NAND controller related registers (only required with the
27 - dmas: shall reference DMA channel associated to the NAND controller.
35 Children nodes represent the available NAND chips.
52 the NAND chip. This value may be overwritten with nand-ecc-strength
55 - nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
|
| H A D | gpio-control-nand.txt | 1 GPIO assisted NAND flash
3 The GPIO assisted NAND flash uses a memory mapped interface to
4 read/write the NAND commands and data and GPIO pins for the control
10 resource describes the data bus connected to the NAND flash and all accesses
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
24 the GPIO's and the NAND flash data bus. If present, then after changing
|
| /OK3568_Linux_fs/kernel/drivers/pinctrl/tegra/ |
| H A D | pinctrl-tegra30.c | 2197 …PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, …
2222 …PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, …
2223 …PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, …
2224 …PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, …
2225 …PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, …
2226 …PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, …
2227 …PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, RSVD4, 0x3204, N, …
2228 …PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, RSVD4, 0x3208, N, …
2229 …PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, RSVD4, 0x320c, N, …
2230 …PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, RSVD4, 0x3210, N, …
[all …]
|
| /OK3568_Linux_fs/u-boot/drivers/rknand/ |
| H A D | Kconfig | 8 bool "Rockchip NAND FLASH device support"
12 This option enables support for Rockchip NAND FLASH devices.
13 It supports block interface(with rk ftl) to read and write NAND FLASH.
20 This option enables support for Rockchip NAND FLASH devices.
22 NAND FLASH.
|
| /OK3568_Linux_fs/u-boot/board/ti/am335x/ |
| H A D | README | 23 worth noting that aside from things such as NAND or MMC only being
38 define additional text blocks (such as for NAND or DFU strings). Also
43 NAND
46 The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In
47 this example to program the NAND we assume that an SD card has been
50 into memory, then written to NAND.
52 Step-1: Building u-boot for NAND boot
53 Set following CONFIGxx options for NAND device.
54 CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page
55 CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page
[all …]
|
| /OK3568_Linux_fs/u-boot/doc/device-tree-bindings/nand/ |
| H A D | nvidia,tegra20-nand.txt | 1 NAND Flash
9 The device node for a NAND flash device is as follows:
17 Nvidia NAND Controller
20 The device node for a NAND flash controller is as follows:
26 nvidia,nand-width : bus width of the NAND device in bits
28 - nvidia,nand-timing : Timing parameters for the NAND. Each is in ns.
|
| /OK3568_Linux_fs/u-boot/board/phytec/pcm058/ |
| H A D | README | 5 The SOM is sold in two versions, with eMMC or with NAND. Support
6 here is for the SOM with NAND.
23 The SOM can boot from NAND or from SD-Card, having the SPI-NOR
26 NAND and SD.
28 DIP-1 set to off: Boot first from NAND, then try SPI
34 device where SPL was loaded (SD or SPI). Booting from NAND is
|
| /OK3568_Linux_fs/kernel/drivers/mtd/rknand/ |
| H A D | Kconfig | 7 tristate "RK NAND Device Support"
11 RK NAND Device Support
15 tristate "RK on-chip NAND Flash Controller driver with FTL"
19 This enables the RK28xx on-chip NAND flash controller and NFTL driver.
44 Determines the verbosity level of the MTD NAND debugging messages.
|
| /OK3568_Linux_fs/u-boot/board/freescale/mpc8313erdb/ |
| H A D | README | 18 To boot the image at the beginning of NAND flash, use these
28 When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
38 0xe280_0000 0xe280_7fff NAND FLASH (CS1) 32K
44 When booting from NAND, NAND flash is CS0 and NOR flash
67 NAND_33 - 33 MHz oscillator, boot from NAND flash
68 NAND_66 - 66 MHz oscillator, boot from NAND flash)
86 NAND flash:
|
| /OK3568_Linux_fs/u-boot/board/nvidia/cardhu/ |
| H A D | pinmux-config-cardhu.h | 205 DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
289 DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT),
292 DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT),
310 DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT),
311 DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
312 DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
313 DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT),
314 DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
315 DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
316 DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
[all …]
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| /OK3568_Linux_fs/u-boot/board/toradex/apalis_t30/ |
| H A D | pinmux-config-apalis_t30.h | 215 DEFAULT_PINMUX(GMI_AD10_PH2, NAND, DOWN, TRISTATE, OUTPUT), /* NC */
303 DEFAULT_PINMUX(GMI_AD12_PH4, NAND, DOWN, TRISTATE, OUTPUT), /* NC */
304 DEFAULT_PINMUX(GMI_AD14_PH6, NAND, DOWN, TRISTATE, OUTPUT), /* NC */
311 DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, DOWN, TRISTATE, OUTPUT),
312 DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, DOWN, TRISTATE, OUTPUT),
313 DEFAULT_PINMUX(GMI_CLK_PK1, NAND, DOWN, TRISTATE, OUTPUT),
314 DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, DOWN, TRISTATE, OUTPUT),
315 DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, DOWN, TRISTATE, OUTPUT),
316 DEFAULT_PINMUX(GMI_AD0_PG0, NAND, DOWN, TRISTATE, OUTPUT),
317 DEFAULT_PINMUX(GMI_AD1_PG1, NAND, DOWN, TRISTATE, OUTPUT),
[all …]
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| /OK3568_Linux_fs/u-boot/board/toradex/colibri_t30/ |
| H A D | pinmux-config-colibri_t30.h | 206 DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
303 DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT),
306 DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT),
324 DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT),
325 DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
326 DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
327 DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT),
328 DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
329 DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
330 DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
[all …]
|