1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _PINMUX_CONFIG_CARDHU_H_ 8*4882a593Smuzhiyun #define _PINMUX_CONFIG_CARDHU_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ 11*4882a593Smuzhiyun { \ 12*4882a593Smuzhiyun .pingrp = PMUX_PINGRP_##_pingrp, \ 13*4882a593Smuzhiyun .func = PMUX_FUNC_##_mux, \ 14*4882a593Smuzhiyun .pull = PMUX_PULL_##_pull, \ 15*4882a593Smuzhiyun .tristate = PMUX_TRI_##_tri, \ 16*4882a593Smuzhiyun .io = PMUX_PIN_##_io, \ 17*4882a593Smuzhiyun .lock = PMUX_PIN_LOCK_DEFAULT, \ 18*4882a593Smuzhiyun .od = PMUX_PIN_OD_DEFAULT, \ 19*4882a593Smuzhiyun .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ 20*4882a593Smuzhiyun } 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ 23*4882a593Smuzhiyun { \ 24*4882a593Smuzhiyun .pingrp = PMUX_PINGRP_##_pingrp, \ 25*4882a593Smuzhiyun .func = PMUX_FUNC_##_mux, \ 26*4882a593Smuzhiyun .pull = PMUX_PULL_##_pull, \ 27*4882a593Smuzhiyun .tristate = PMUX_TRI_##_tri, \ 28*4882a593Smuzhiyun .io = PMUX_PIN_##_io, \ 29*4882a593Smuzhiyun .lock = PMUX_PIN_LOCK_##_lock, \ 30*4882a593Smuzhiyun .od = PMUX_PIN_OD_##_od, \ 31*4882a593Smuzhiyun .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ 32*4882a593Smuzhiyun } 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ 35*4882a593Smuzhiyun { \ 36*4882a593Smuzhiyun .pingrp = PMUX_PINGRP_##_pingrp, \ 37*4882a593Smuzhiyun .func = PMUX_FUNC_##_mux, \ 38*4882a593Smuzhiyun .pull = PMUX_PULL_##_pull, \ 39*4882a593Smuzhiyun .tristate = PMUX_TRI_##_tri, \ 40*4882a593Smuzhiyun .io = PMUX_PIN_##_io, \ 41*4882a593Smuzhiyun .lock = PMUX_PIN_LOCK_##_lock, \ 42*4882a593Smuzhiyun .od = PMUX_PIN_OD_DEFAULT, \ 43*4882a593Smuzhiyun .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ 44*4882a593Smuzhiyun } 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ 47*4882a593Smuzhiyun { \ 48*4882a593Smuzhiyun .drvgrp = PMUX_DRVGRP_##_drvgrp, \ 49*4882a593Smuzhiyun .slwf = _slwf, \ 50*4882a593Smuzhiyun .slwr = _slwr, \ 51*4882a593Smuzhiyun .drvup = _drvup, \ 52*4882a593Smuzhiyun .drvdn = _drvdn, \ 53*4882a593Smuzhiyun .lpmd = PMUX_LPMD_##_lpmd, \ 54*4882a593Smuzhiyun .schmt = PMUX_SCHMT_##_schmt, \ 55*4882a593Smuzhiyun .hsm = PMUX_HSM_##_hsm, \ 56*4882a593Smuzhiyun } 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun static struct pmux_pingrp_config tegra3_pinmux_common[] = { 59*4882a593Smuzhiyun /* SDMMC1 pinmux */ 60*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), 61*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), 62*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), 63*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), 64*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), 65*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* SDMMC3 pinmux */ 68*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), 69*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), 70*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), 71*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), 72*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), 73*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), 74*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_DAT6_PD3, RSVD1, NORMAL, NORMAL, INPUT), 75*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD1, NORMAL, NORMAL, INPUT), 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* SDMMC4 pinmux */ 78*4882a593Smuzhiyun LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 79*4882a593Smuzhiyun LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 80*4882a593Smuzhiyun LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 81*4882a593Smuzhiyun LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 82*4882a593Smuzhiyun LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 83*4882a593Smuzhiyun LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 84*4882a593Smuzhiyun LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 85*4882a593Smuzhiyun LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 86*4882a593Smuzhiyun LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 87*4882a593Smuzhiyun LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 88*4882a593Smuzhiyun LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* I2C1 pinmux */ 91*4882a593Smuzhiyun I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 92*4882a593Smuzhiyun I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* I2C2 pinmux */ 95*4882a593Smuzhiyun I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 96*4882a593Smuzhiyun I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* I2C3 pinmux */ 99*4882a593Smuzhiyun I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 100*4882a593Smuzhiyun I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* I2C4 pinmux */ 103*4882a593Smuzhiyun I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 104*4882a593Smuzhiyun I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* Power I2C pinmux */ 107*4882a593Smuzhiyun I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 108*4882a593Smuzhiyun I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT), 111*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT), 112*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT), 113*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT), 114*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT), 115*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT), 116*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), 117*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT), 118*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT), 119*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT), 120*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT), 121*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT), 122*4882a593Smuzhiyun DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), 123*4882a593Smuzhiyun DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), 124*4882a593Smuzhiyun DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), 125*4882a593Smuzhiyun DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), 126*4882a593Smuzhiyun DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT), 127*4882a593Smuzhiyun DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, OUTPUT), 128*4882a593Smuzhiyun DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT), 129*4882a593Smuzhiyun DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT), 130*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT), 131*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT), 132*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT), 133*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT), 134*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT), 135*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT), 136*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT), 137*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT), 138*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT), 139*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), 140*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), 141*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), 142*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), 143*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), 144*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), 145*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), 146*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), 147*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), 148*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), 149*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), 150*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), 151*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), 152*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), 153*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), 154*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), 155*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), 156*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), 157*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), 158*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), 159*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), 160*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), 161*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), 162*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), 163*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), 164*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), 165*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), 166*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), 167*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT), 168*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT), 169*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT), 170*4882a593Smuzhiyun DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT), 171*4882a593Smuzhiyun DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT), 172*4882a593Smuzhiyun LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 173*4882a593Smuzhiyun LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 174*4882a593Smuzhiyun LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 175*4882a593Smuzhiyun LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 176*4882a593Smuzhiyun LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), 177*4882a593Smuzhiyun LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 178*4882a593Smuzhiyun LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 179*4882a593Smuzhiyun LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 180*4882a593Smuzhiyun LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), 181*4882a593Smuzhiyun DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), 182*4882a593Smuzhiyun DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), 183*4882a593Smuzhiyun DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), 184*4882a593Smuzhiyun DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), 185*4882a593Smuzhiyun DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), 186*4882a593Smuzhiyun DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), 187*4882a593Smuzhiyun DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), 188*4882a593Smuzhiyun DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), 189*4882a593Smuzhiyun DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT), 190*4882a593Smuzhiyun DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT), 191*4882a593Smuzhiyun DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT), 192*4882a593Smuzhiyun DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT), 193*4882a593Smuzhiyun DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT), 194*4882a593Smuzhiyun DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT), 195*4882a593Smuzhiyun DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT), 196*4882a593Smuzhiyun DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), 197*4882a593Smuzhiyun DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), 198*4882a593Smuzhiyun DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), 199*4882a593Smuzhiyun DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), 200*4882a593Smuzhiyun DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), 201*4882a593Smuzhiyun DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT), 202*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, NORMAL, NORMAL, INPUT), 203*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */ 204*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */ 205*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */ 206*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT), 207*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT), 208*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT), 209*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT), 210*4882a593Smuzhiyun DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, NORMAL, INPUT), 211*4882a593Smuzhiyun DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, INPUT), 212*4882a593Smuzhiyun DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT), 213*4882a593Smuzhiyun DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT), 214*4882a593Smuzhiyun DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT), 215*4882a593Smuzhiyun DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT), 216*4882a593Smuzhiyun DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT), 217*4882a593Smuzhiyun DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT), 218*4882a593Smuzhiyun DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun /* KBC keys */ 221*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT), 222*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), 223*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT), 224*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT), 225*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW4_PR4, KBC, UP, NORMAL, INPUT), 226*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW5_PR5, KBC, UP, NORMAL, INPUT), 227*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT), 228*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT), 229*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), 230*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT), 231*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT), 232*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW11_PS3, KBC, UP, NORMAL, INPUT), 233*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW12_PS4, KBC, UP, NORMAL, INPUT), 234*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT), 235*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT), 236*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT), 237*4882a593Smuzhiyun DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), 238*4882a593Smuzhiyun DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), 239*4882a593Smuzhiyun DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), 240*4882a593Smuzhiyun DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT), 241*4882a593Smuzhiyun DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT), 242*4882a593Smuzhiyun DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT), 243*4882a593Smuzhiyun DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT), 244*4882a593Smuzhiyun DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT), 245*4882a593Smuzhiyun DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT), 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), 248*4882a593Smuzhiyun DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), 249*4882a593Smuzhiyun DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), 250*4882a593Smuzhiyun DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), 251*4882a593Smuzhiyun DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT), 252*4882a593Smuzhiyun DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), 253*4882a593Smuzhiyun DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), 254*4882a593Smuzhiyun DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT), 255*4882a593Smuzhiyun DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT), 256*4882a593Smuzhiyun DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT), 257*4882a593Smuzhiyun DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT), 258*4882a593Smuzhiyun DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), 259*4882a593Smuzhiyun DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT), 260*4882a593Smuzhiyun DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), 261*4882a593Smuzhiyun DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT), 264*4882a593Smuzhiyun DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), 265*4882a593Smuzhiyun DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), 266*4882a593Smuzhiyun DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), 267*4882a593Smuzhiyun DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), 268*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT), 269*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT), 270*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT), 271*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), 272*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), 273*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT), 274*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), 275*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), 276*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), 277*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), 278*4882a593Smuzhiyun DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), 279*4882a593Smuzhiyun DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun /* GPIOs */ 282*4882a593Smuzhiyun /* SDMMC1 CD gpio */ 283*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT), 284*4882a593Smuzhiyun /* SDMMC1 WP gpio */ 285*4882a593Smuzhiyun LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE), 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun /* Touch panel GPIO */ 288*4882a593Smuzhiyun /* Touch IRQ */ 289*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT), 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun /* Touch RESET */ 292*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT), 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun /* Power rails GPIO */ 295*4882a593Smuzhiyun DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT), 296*4882a593Smuzhiyun DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT), 297*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), 298*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT), 299*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT), 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), 302*4882a593Smuzhiyun LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 303*4882a593Smuzhiyun LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 304*4882a593Smuzhiyun LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE), 305*4882a593Smuzhiyun LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 306*4882a593Smuzhiyun LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 307*4882a593Smuzhiyun }; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun static struct pmux_pingrp_config unused_pins_lowpower[] = { 310*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT), 311*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT), 312*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT), 313*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT), 314*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT), 315*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT), 316*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT), 317*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT), 318*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT), 319*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT), 320*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT), 321*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT), 322*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT), 323*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT), 324*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT), 325*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT), 326*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT), 327*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT), 328*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT), 329*4882a593Smuzhiyun }; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun static struct pmux_drvgrp_config cardhu_padctrl[] = { 332*4882a593Smuzhiyun /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ 333*4882a593Smuzhiyun DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ 334*4882a593Smuzhiyun SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), 335*4882a593Smuzhiyun }; 336*4882a593Smuzhiyun #endif /* _PINMUX_CONFIG_CARDHU_H_ */ 337