1*4882a593SmuzhiyunNVIDIA Tegra NAND Flash controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Must be one of: 5*4882a593Smuzhiyun - "nvidia,tegra20-nand" 6*4882a593Smuzhiyun- reg: MMIO address range 7*4882a593Smuzhiyun- interrupts: interrupt output of the NFC controller 8*4882a593Smuzhiyun- clocks: Must contain an entry for each entry in clock-names. 9*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 10*4882a593Smuzhiyun- clock-names: Must include the following entries: 11*4882a593Smuzhiyun - nand 12*4882a593Smuzhiyun- resets: Must contain an entry for each entry in reset-names. 13*4882a593Smuzhiyun See ../reset/reset.txt for details. 14*4882a593Smuzhiyun- reset-names: Must include the following entries: 15*4882a593Smuzhiyun - nand 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional children nodes: 18*4882a593SmuzhiyunIndividual NAND chips are children of the NAND controller node. Currently 19*4882a593Smuzhiyunonly one NAND chip supported. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunRequired children node properties: 22*4882a593Smuzhiyun- reg: An integer ranging from 1 to 6 representing the CS line to use. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunOptional children node properties: 25*4882a593Smuzhiyun- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only 26*4882a593Smuzhiyun "hw" is supported. 27*4882a593Smuzhiyun- nand-ecc-algo: string, algorithm of NAND ECC. 28*4882a593Smuzhiyun Supported values with "hw" ECC mode are: "rs", "bch". 29*4882a593Smuzhiyun- nand-bus-width : See nand-controller.yaml 30*4882a593Smuzhiyun- nand-on-flash-bbt: See nand-controller.yaml 31*4882a593Smuzhiyun- nand-ecc-strength: integer representing the number of bits to correct 32*4882a593Smuzhiyun per ECC step (always 512). Supported strength using HW ECC 33*4882a593Smuzhiyun modes are: 34*4882a593Smuzhiyun - RS: 4, 6, 8 35*4882a593Smuzhiyun - BCH: 4, 8, 14, 16 36*4882a593Smuzhiyun- nand-ecc-maximize: See nand-controller.yaml 37*4882a593Smuzhiyun- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM 38*4882a593Smuzhiyun are chosen. 39*4882a593Smuzhiyun- wp-gpios: GPIO specifier for the write protect pin. 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunOptional child node of NAND chip nodes: 42*4882a593SmuzhiyunPartitions: see partition.txt 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun Example: 45*4882a593Smuzhiyun nand-controller@70008000 { 46*4882a593Smuzhiyun compatible = "nvidia,tegra20-nand"; 47*4882a593Smuzhiyun reg = <0x70008000 0x100>; 48*4882a593Smuzhiyun interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 49*4882a593Smuzhiyun clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; 50*4882a593Smuzhiyun clock-names = "nand"; 51*4882a593Smuzhiyun resets = <&tegra_car 13>; 52*4882a593Smuzhiyun reset-names = "nand"; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun nand@0 { 55*4882a593Smuzhiyun reg = <0>; 56*4882a593Smuzhiyun #address-cells = <1>; 57*4882a593Smuzhiyun #size-cells = <1>; 58*4882a593Smuzhiyun nand-bus-width = <8>; 59*4882a593Smuzhiyun nand-on-flash-bbt; 60*4882a593Smuzhiyun nand-ecc-algo = "bch"; 61*4882a593Smuzhiyun nand-ecc-strength = <8>; 62*4882a593Smuzhiyun wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun }; 65