Lines Matching refs:NAND

1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
19                      the core NAND controller, of the following form:
35 - reg              : the register start and length for NAND register region.
37                      (optional) NAND flash cache range (if at non-standard offset)
41 - interrupts       : The NAND CTLRDY interrupt, (if Flash DMA is available)
45                      May be "nand", if the SoC has the individual NAND
52 - clock                     : reference to the clock for the NAND controller
59  -- Additional SoC-specific NAND controller properties --
61 The NAND controller is integrated differently on the variety of SoCs on which it
63 with which to control the 8 exposed NAND interrupts, as well as hardware for
67 ways, sometimes with registers that lump multiple NAND-related functions
70 we define additional 'compatible' properties and associated register resources within the NAND cont…
95 * NAND chip-select
98 to represent enabled chip-selects which (may) contain NAND flash chips. Their
119                               the flash geometry (particularly the NAND page
121                               from NAND, the boot controller has only a limited