xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/marvell-nand.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunMarvell NAND Flash Controller (NFC)
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunRequired properties:
4*4882a593Smuzhiyun- compatible: can be one of the following:
5*4882a593Smuzhiyun    * "marvell,armada-8k-nand-controller"
6*4882a593Smuzhiyun    * "marvell,armada370-nand-controller"
7*4882a593Smuzhiyun    * "marvell,pxa3xx-nand-controller"
8*4882a593Smuzhiyun    * "marvell,armada-8k-nand" (deprecated)
9*4882a593Smuzhiyun    * "marvell,armada370-nand" (deprecated)
10*4882a593Smuzhiyun    * "marvell,pxa3xx-nand" (deprecated)
11*4882a593Smuzhiyun  Compatibles marked deprecated support only the old bindings described
12*4882a593Smuzhiyun  at the bottom.
13*4882a593Smuzhiyun- reg: NAND flash controller memory area.
14*4882a593Smuzhiyun- #address-cells: shall be set to 1. Encode the NAND CS.
15*4882a593Smuzhiyun- #size-cells: shall be set to 0.
16*4882a593Smuzhiyun- interrupts: shall define the NAND controller interrupt.
17*4882a593Smuzhiyun- clocks: shall reference the NAND controller clocks, the second one is
18*4882a593Smuzhiyun  is only needed for the Armada 7K/8K SoCs
19*4882a593Smuzhiyun- clock-names: mandatory if there is a second clock, in this case there
20*4882a593Smuzhiyun  should be one clock named "core" and another one named "reg"
21*4882a593Smuzhiyun- marvell,system-controller: Set to retrieve the syscon node that handles
22*4882a593Smuzhiyun  NAND controller related registers (only required with the
23*4882a593Smuzhiyun  "marvell,armada-8k-nand[-controller]" compatibles).
24*4882a593Smuzhiyun
25*4882a593SmuzhiyunOptional properties:
26*4882a593Smuzhiyun- label: see partition.txt. New platforms shall omit this property.
27*4882a593Smuzhiyun- dmas: shall reference DMA channel associated to the NAND controller.
28*4882a593Smuzhiyun  This property is only used with "marvell,pxa3xx-nand[-controller]"
29*4882a593Smuzhiyun  compatible strings.
30*4882a593Smuzhiyun- dma-names: shall be "rxtx".
31*4882a593Smuzhiyun  This property is only used with "marvell,pxa3xx-nand[-controller]"
32*4882a593Smuzhiyun  compatible strings.
33*4882a593Smuzhiyun
34*4882a593SmuzhiyunOptional children nodes:
35*4882a593SmuzhiyunChildren nodes represent the available NAND chips.
36*4882a593Smuzhiyun
37*4882a593SmuzhiyunRequired properties:
38*4882a593Smuzhiyun- reg: shall contain the native Chip Select ids (0-3).
39*4882a593Smuzhiyun- nand-rb: see nand-controller.yaml (0-1).
40*4882a593Smuzhiyun
41*4882a593SmuzhiyunOptional properties:
42*4882a593Smuzhiyun- marvell,nand-keep-config: orders the driver not to take the timings
43*4882a593Smuzhiyun  from the core and leaving them completely untouched. Bootloader
44*4882a593Smuzhiyun  timings will then be used.
45*4882a593Smuzhiyun- label: MTD name.
46*4882a593Smuzhiyun- nand-on-flash-bbt: see nand-controller.yaml.
47*4882a593Smuzhiyun- nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
48*4882a593Smuzhiyun- nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when
49*4882a593Smuzhiyun  not using hardware ECC. Howerver, it may be added when using hardware
50*4882a593Smuzhiyun  ECC for clarification but will be ignored by the driver because ECC
51*4882a593Smuzhiyun  mode is chosen depending on the page size and the strength required by
52*4882a593Smuzhiyun  the NAND chip. This value may be overwritten with nand-ecc-strength
53*4882a593Smuzhiyun  property.
54*4882a593Smuzhiyun- nand-ecc-strength: see nand-controller.yaml.
55*4882a593Smuzhiyun- nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
56*4882a593Smuzhiyun  use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual
57*4882a593Smuzhiyun  step size will shrink or grow in order to fit the required strength.
58*4882a593Smuzhiyun  Step sizes are not completely random for all and follow certain
59*4882a593Smuzhiyun  patterns described in AN-379, "Marvell SoC NFC ECC".
60*4882a593Smuzhiyun
61*4882a593SmuzhiyunSee Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
62*4882a593Smuzhiyungeneric bindings.
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun
65*4882a593SmuzhiyunExample:
66*4882a593Smuzhiyunnand_controller: nand-controller@d0000 {
67*4882a593Smuzhiyun	compatible = "marvell,armada370-nand-controller";
68*4882a593Smuzhiyun	reg = <0xd0000 0x54>;
69*4882a593Smuzhiyun	#address-cells = <1>;
70*4882a593Smuzhiyun	#size-cells = <0>;
71*4882a593Smuzhiyun	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
72*4882a593Smuzhiyun	clocks = <&coredivclk 0>;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun	nand@0 {
75*4882a593Smuzhiyun		reg = <0>;
76*4882a593Smuzhiyun		label = "main-storage";
77*4882a593Smuzhiyun		nand-rb = <0>;
78*4882a593Smuzhiyun		nand-ecc-mode = "hw";
79*4882a593Smuzhiyun		marvell,nand-keep-config;
80*4882a593Smuzhiyun		nand-on-flash-bbt;
81*4882a593Smuzhiyun		nand-ecc-strength = <4>;
82*4882a593Smuzhiyun		nand-ecc-step-size = <512>;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun		partitions {
85*4882a593Smuzhiyun			compatible = "fixed-partitions";
86*4882a593Smuzhiyun			#address-cells = <1>;
87*4882a593Smuzhiyun			#size-cells = <1>;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun			partition@0 {
90*4882a593Smuzhiyun				label = "Rootfs";
91*4882a593Smuzhiyun				reg = <0x00000000 0x40000000>;
92*4882a593Smuzhiyun			};
93*4882a593Smuzhiyun		};
94*4882a593Smuzhiyun	};
95*4882a593Smuzhiyun};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun
98*4882a593SmuzhiyunNote on legacy bindings: One can find, in not-updated device trees,
99*4882a593Smuzhiyunbindings slightly different than described above with other properties
100*4882a593Smuzhiyundescribed below as well as the partitions node at the root of a so
101*4882a593Smuzhiyuncalled "nand" node (without clear controller/chip separation).
102*4882a593Smuzhiyun
103*4882a593SmuzhiyunLegacy properties:
104*4882a593Smuzhiyun- marvell,nand-enable-arbiter: To enable the arbiter, all boards blindly
105*4882a593Smuzhiyun  used it, this bit was set by the bootloader for many boards and even if
106*4882a593Smuzhiyun  it is marked reserved in several datasheets, it might be needed to set
107*4882a593Smuzhiyun  it (otherwise it is harmless) so whether or not this property is set,
108*4882a593Smuzhiyun  the bit is selected by the driver.
109*4882a593Smuzhiyun- num-cs: Number of chip-select lines to use, all boards blindly set 1
110*4882a593Smuzhiyun  to this and for a reason, other values would have failed. The value of
111*4882a593Smuzhiyun  this property is ignored.
112*4882a593Smuzhiyun
113*4882a593SmuzhiyunExample:
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun	nand0: nand@43100000 {
116*4882a593Smuzhiyun		compatible = "marvell,pxa3xx-nand";
117*4882a593Smuzhiyun		reg = <0x43100000 90>;
118*4882a593Smuzhiyun		interrupts = <45>;
119*4882a593Smuzhiyun		dmas = <&pdma 97 0>;
120*4882a593Smuzhiyun		dma-names = "rxtx";
121*4882a593Smuzhiyun		#address-cells = <1>;
122*4882a593Smuzhiyun		marvell,nand-keep-config;
123*4882a593Smuzhiyun		marvell,nand-enable-arbiter;
124*4882a593Smuzhiyun		num-cs = <1>;
125*4882a593Smuzhiyun		/* Partitions (optional) */
126*4882a593Smuzhiyun       };
127