1*4882a593SmuzhiyunGPIO assisted NAND flash 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe GPIO assisted NAND flash uses a memory mapped interface to 4*4882a593Smuzhiyunread/write the NAND commands and data and GPIO pins for the control 5*4882a593Smuzhiyunsignals. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible : "gpio-control-nand" 9*4882a593Smuzhiyun- reg : should specify localbus chip select and size used for the chip. The 10*4882a593Smuzhiyun resource describes the data bus connected to the NAND flash and all accesses 11*4882a593Smuzhiyun are made in native endianness. 12*4882a593Smuzhiyun- #address-cells, #size-cells : Must be present if the device has sub-nodes 13*4882a593Smuzhiyun representing partitions. 14*4882a593Smuzhiyun- gpios : Specifies the GPIO pins to control the NAND device. The order of 15*4882a593Smuzhiyun GPIO references is: RDY, nCE, ALE, CLE, and nWP. nCE and nWP are optional. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties: 18*4882a593Smuzhiyun- bank-width : Width (in bytes) of the device. If not present, the width 19*4882a593Smuzhiyun defaults to 1 byte. 20*4882a593Smuzhiyun- chip-delay : chip dependent delay for transferring data from array to 21*4882a593Smuzhiyun read registers (tR). If not present then a default of 20us is used. 22*4882a593Smuzhiyun- gpio-control-nand,io-sync-reg : A 64-bit physical address for a read 23*4882a593Smuzhiyun location used to guard against bus reordering with regards to accesses to 24*4882a593Smuzhiyun the GPIO's and the NAND flash data bus. If present, then after changing 25*4882a593Smuzhiyun GPIO state and before and after command byte writes, this register will be 26*4882a593Smuzhiyun read to ensure that the GPIO accesses have completed. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunThe device tree may optionally contain sub-nodes describing partitions of the 29*4882a593Smuzhiyunaddress space. See partition.txt for more detail. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunExamples: 32*4882a593Smuzhiyun 33*4882a593Smuzhiyungpio-nand@1,0 { 34*4882a593Smuzhiyun compatible = "gpio-control-nand"; 35*4882a593Smuzhiyun reg = <1 0x0000 0x2>; 36*4882a593Smuzhiyun #address-cells = <1>; 37*4882a593Smuzhiyun #size-cells = <1>; 38*4882a593Smuzhiyun gpios = <&banka 1 0>, /* RDY */ 39*4882a593Smuzhiyun <0>, /* nCE */ 40*4882a593Smuzhiyun <&banka 3 0>, /* ALE */ 41*4882a593Smuzhiyun <&banka 4 0>, /* CLE */ 42*4882a593Smuzhiyun <0>; /* nWP */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun partition@0 { 45*4882a593Smuzhiyun ... 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun}; 48