1*4882a593Smuzhiyun* Qualcomm NAND controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: must be one of the following: 5*4882a593Smuzhiyun * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x 6*4882a593Smuzhiyun SoC and it uses ADM DMA 7*4882a593Smuzhiyun * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in 8*4882a593Smuzhiyun IPQ4019 SoC and it uses BAM DMA 9*4882a593Smuzhiyun * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in 10*4882a593Smuzhiyun IPQ8074 SoC and it uses BAM DMA 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- reg: MMIO address range 13*4882a593Smuzhiyun- clocks: must contain core clock and always on clock 14*4882a593Smuzhiyun- clock-names: must contain "core" for the core clock and "aon" for the 15*4882a593Smuzhiyun always on clock 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunEBI2 specific properties: 18*4882a593Smuzhiyun- dmas: DMA specifier, consisting of a phandle to the ADM DMA 19*4882a593Smuzhiyun controller node and the channel number to be used for 20*4882a593Smuzhiyun NAND. Refer to dma.txt and qcom_adm.txt for more details 21*4882a593Smuzhiyun- dma-names: must be "rxtx" 22*4882a593Smuzhiyun- qcom,cmd-crci: must contain the ADM command type CRCI block instance 23*4882a593Smuzhiyun number specified for the NAND controller on the given 24*4882a593Smuzhiyun platform 25*4882a593Smuzhiyun- qcom,data-crci: must contain the ADM data type CRCI block instance 26*4882a593Smuzhiyun number specified for the NAND controller on the given 27*4882a593Smuzhiyun platform 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunQPIC specific properties: 30*4882a593Smuzhiyun- dmas: DMA specifier, consisting of a phandle to the BAM DMA 31*4882a593Smuzhiyun and the channel number to be used for NAND. Refer to 32*4882a593Smuzhiyun dma.txt, qcom_bam_dma.txt for more details 33*4882a593Smuzhiyun- dma-names: must contain all 3 channel names : "tx", "rx", "cmd" 34*4882a593Smuzhiyun- #address-cells: <1> - subnodes give the chip-select number 35*4882a593Smuzhiyun- #size-cells: <0> 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun* NAND chip-select 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunEach controller may contain one or more subnodes to represent enabled 40*4882a593Smuzhiyunchip-selects which (may) contain NAND flash chips. Their properties are as 41*4882a593Smuzhiyunfollows. 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunRequired properties: 44*4882a593Smuzhiyun- reg: a single integer representing the chip-select 45*4882a593Smuzhiyun number (e.g., 0, 1, 2, etc.) 46*4882a593Smuzhiyun- #address-cells: see partition.txt 47*4882a593Smuzhiyun- #size-cells: see partition.txt 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunOptional properties: 50*4882a593Smuzhiyun- nand-bus-width: see nand-controller.yaml 51*4882a593Smuzhiyun- nand-ecc-strength: see nand-controller.yaml. If not specified, then ECC strength will 52*4882a593Smuzhiyun be used according to chip requirement and available 53*4882a593Smuzhiyun OOB size. 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunEach nandcs device node may optionally contain a 'partitions' sub-node, which 56*4882a593Smuzhiyunfurther contains sub-nodes describing the flash partition mapping. See 57*4882a593Smuzhiyunpartition.txt for more detail. 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunExample: 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunnand-controller@1ac00000 { 62*4882a593Smuzhiyun compatible = "qcom,ipq806x-nand"; 63*4882a593Smuzhiyun reg = <0x1ac00000 0x800>; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun clocks = <&gcc EBI2_CLK>, 66*4882a593Smuzhiyun <&gcc EBI2_AON_CLK>; 67*4882a593Smuzhiyun clock-names = "core", "aon"; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun dmas = <&adm_dma 3>; 70*4882a593Smuzhiyun dma-names = "rxtx"; 71*4882a593Smuzhiyun qcom,cmd-crci = <15>; 72*4882a593Smuzhiyun qcom,data-crci = <3>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #address-cells = <1>; 75*4882a593Smuzhiyun #size-cells = <0>; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun nand@0 { 78*4882a593Smuzhiyun reg = <0>; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun nand-ecc-strength = <4>; 81*4882a593Smuzhiyun nand-bus-width = <8>; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun partitions { 84*4882a593Smuzhiyun compatible = "fixed-partitions"; 85*4882a593Smuzhiyun #address-cells = <1>; 86*4882a593Smuzhiyun #size-cells = <1>; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun partition@0 { 89*4882a593Smuzhiyun label = "boot-nand"; 90*4882a593Smuzhiyun reg = <0 0x58a0000>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun partition@58a0000 { 94*4882a593Smuzhiyun label = "fs-nand"; 95*4882a593Smuzhiyun reg = <0x58a0000 0x4000000>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun}; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyunnand-controller@79b0000 { 102*4882a593Smuzhiyun compatible = "qcom,ipq4019-nand"; 103*4882a593Smuzhiyun reg = <0x79b0000 0x1000>; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun clocks = <&gcc GCC_QPIC_CLK>, 106*4882a593Smuzhiyun <&gcc GCC_QPIC_AHB_CLK>; 107*4882a593Smuzhiyun clock-names = "core", "aon"; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun dmas = <&qpicbam 0>, 110*4882a593Smuzhiyun <&qpicbam 1>, 111*4882a593Smuzhiyun <&qpicbam 2>; 112*4882a593Smuzhiyun dma-names = "tx", "rx", "cmd"; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #address-cells = <1>; 115*4882a593Smuzhiyun #size-cells = <0>; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun nand@0 { 118*4882a593Smuzhiyun reg = <0>; 119*4882a593Smuzhiyun nand-ecc-strength = <4>; 120*4882a593Smuzhiyun nand-bus-width = <8>; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun partitions { 123*4882a593Smuzhiyun compatible = "fixed-partitions"; 124*4882a593Smuzhiyun #address-cells = <1>; 125*4882a593Smuzhiyun #size-cells = <1>; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun partition@0 { 128*4882a593Smuzhiyun label = "boot-nand"; 129*4882a593Smuzhiyun reg = <0 0x58a0000>; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun partition@58a0000 { 133*4882a593Smuzhiyun label = "fs-nand"; 134*4882a593Smuzhiyun reg = <0x58a0000 0x4000000>; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun}; 139