1*4882a593SmuzhiyunST Microelectronics Flexible Static Memory Controller (FSMC) 2*4882a593SmuzhiyunNAND Interface 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand" 6*4882a593Smuzhiyun- reg : Address range of the mtd chip 7*4882a593Smuzhiyun- reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd" 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunOptional properties: 10*4882a593Smuzhiyun- bank-width : Width (in bytes) of the device. If not present, the width 11*4882a593Smuzhiyun defaults to 1 byte 12*4882a593Smuzhiyun- nand-skip-bbtscan: Indicates the BBT scanning should be skipped 13*4882a593Smuzhiyun- timings: array of 6 bytes for NAND timings. The meanings of these bytes 14*4882a593Smuzhiyun are: 15*4882a593Smuzhiyun byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits 16*4882a593Smuzhiyun are valid. Zero means one clockcycle, 15 means 16 clock 17*4882a593Smuzhiyun cycles. 18*4882a593Smuzhiyun byte 1 TAR : ALE to RE delay, 4 bits are valid. Same format as TCLR. 19*4882a593Smuzhiyun byte 2 THIZ : number of HCLK clock cycles during which the data bus is 20*4882a593Smuzhiyun kept in Hi-Z (tristate) after the start of a write access. 21*4882a593Smuzhiyun Only valid for write transactions. Zero means zero cycles, 22*4882a593Smuzhiyun 255 means 255 cycles. 23*4882a593Smuzhiyun byte 3 THOLD : number of HCLK clock cycles to hold the address (and data 24*4882a593Smuzhiyun when writing) after the command deassertation. Zero means 25*4882a593Smuzhiyun one cycle, 255 means 256 cycles. 26*4882a593Smuzhiyun byte 4 TWAIT : number of HCLK clock cycles to assert the command to the 27*4882a593Smuzhiyun NAND flash in response to SMWAITn. Zero means 1 cycle, 28*4882a593Smuzhiyun 255 means 256 cycles. 29*4882a593Smuzhiyun byte 5 TSET : number of HCLK clock cycles to assert the address before the 30*4882a593Smuzhiyun command is asserted. Zero means one cycle, 255 means 256 31*4882a593Smuzhiyun cycles. 32*4882a593Smuzhiyun- bank: default NAND bank to use (0-3 are valid, 0 is the default). 33*4882a593Smuzhiyun- nand-ecc-mode : see nand-controller.yaml 34*4882a593Smuzhiyun- nand-ecc-strength : see nand-controller.yaml 35*4882a593Smuzhiyun- nand-ecc-step-size : see nand-controller.yaml 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunCan support 1-bit HW ECC (default) or if stronger correction is required, 38*4882a593Smuzhiyunsoftware-based BCH. 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExample: 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun fsmc: flash@d1800000 { 43*4882a593Smuzhiyun compatible = "st,spear600-fsmc-nand"; 44*4882a593Smuzhiyun #address-cells = <1>; 45*4882a593Smuzhiyun #size-cells = <1>; 46*4882a593Smuzhiyun reg = <0xd1800000 0x1000 /* FSMC Register */ 47*4882a593Smuzhiyun 0xd2000000 0x0010 /* NAND Base DATA */ 48*4882a593Smuzhiyun 0xd2020000 0x0010 /* NAND Base ADDR */ 49*4882a593Smuzhiyun 0xd2010000 0x0010>; /* NAND Base CMD */ 50*4882a593Smuzhiyun reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun bank-width = <1>; 53*4882a593Smuzhiyun nand-skip-bbtscan; 54*4882a593Smuzhiyun timings = /bits/ 8 <0 0 0 2 3 0>; 55*4882a593Smuzhiyun bank = <1>; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun partition@0 { 58*4882a593Smuzhiyun ... 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61