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Searched refs:CLK_TOP_MSDC50_0_SEL (Results 1 – 13 of 13) sorted by relevance

/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dmt7629-clk.h94 #define CLK_TOP_MSDC50_0_SEL 84 macro
H A Dmt7622-clk.h79 #define CLK_TOP_MSDC50_0_SEL 67 macro
H A Dmt6765-clk.h144 #define CLK_TOP_MSDC50_0_SEL 109 macro
H A Dmt8173-clk.h106 #define CLK_TOP_MSDC50_0_SEL 96 macro
H A Dmt2712-clk.h143 #define CLK_TOP_MSDC50_0_SEL 112 macro
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dmtk-sd.txt69 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mt7629.c511 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
H A Dclk-mt7622.c541 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
H A Dclk-mt8173.c559 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x0070, 16, 4, 23),
H A Dclk-mt6765.c409 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
H A Dclk-mt2712.c767 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/
H A Dmt8173-elm.dtsi373 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
H A Dmt7622.dtsi687 <&topckgen CLK_TOP_MSDC50_0_SEL>;