xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2016 MediaTek Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
7*4882a593Smuzhiyun#include <dt-bindings/input/linux-event-codes.h>
8*4882a593Smuzhiyun#include <dt-bindings/regulator/dlg,da9211-regulator.h>
9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
10*4882a593Smuzhiyun#include "mt8173.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	memory@40000000 {
14*4882a593Smuzhiyun		device_type = "memory";
15*4882a593Smuzhiyun		reg = <0 0x40000000 0 0x80000000>;
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	backlight: backlight {
19*4882a593Smuzhiyun		compatible = "pwm-backlight";
20*4882a593Smuzhiyun		pwms = <&pwm0 0 1000000>;
21*4882a593Smuzhiyun		power-supply = <&bl_fixed_reg>;
22*4882a593Smuzhiyun		enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun		pinctrl-names = "default";
25*4882a593Smuzhiyun		pinctrl-0 = <&disp_pwm0_pins>;
26*4882a593Smuzhiyun		status = "okay";
27*4882a593Smuzhiyun	};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun	bl_fixed_reg: fixedregulator2 {
30*4882a593Smuzhiyun		compatible = "regulator-fixed";
31*4882a593Smuzhiyun		regulator-name = "bl_fixed";
32*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
33*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
34*4882a593Smuzhiyun		startup-delay-us = <1000>;
35*4882a593Smuzhiyun		enable-active-high;
36*4882a593Smuzhiyun		gpio = <&pio 32 GPIO_ACTIVE_HIGH>;
37*4882a593Smuzhiyun		pinctrl-names = "default";
38*4882a593Smuzhiyun		pinctrl-0 = <&bl_fixed_pins>;
39*4882a593Smuzhiyun	};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun	chosen {
42*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
43*4882a593Smuzhiyun	};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	gpio_keys: gpio-keys {
46*4882a593Smuzhiyun		compatible = "gpio-keys";
47*4882a593Smuzhiyun		pinctrl-names = "default";
48*4882a593Smuzhiyun		pinctrl-0 = <&gpio_keys_pins>;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun		lid {
51*4882a593Smuzhiyun			label = "Lid";
52*4882a593Smuzhiyun			gpios = <&pio 69 GPIO_ACTIVE_LOW>;
53*4882a593Smuzhiyun			linux,code = <SW_LID>;
54*4882a593Smuzhiyun			linux,input-type = <EV_SW>;
55*4882a593Smuzhiyun			gpio-key,wakeup;
56*4882a593Smuzhiyun		};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun		power {
59*4882a593Smuzhiyun			label = "Power";
60*4882a593Smuzhiyun			gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
61*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
62*4882a593Smuzhiyun			debounce-interval = <30>;
63*4882a593Smuzhiyun			gpio-key,wakeup;
64*4882a593Smuzhiyun		};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun		tablet_mode {
67*4882a593Smuzhiyun			label = "Tablet_mode";
68*4882a593Smuzhiyun			gpios = <&pio 121 GPIO_ACTIVE_HIGH>;
69*4882a593Smuzhiyun			linux,code = <SW_TABLET_MODE>;
70*4882a593Smuzhiyun			linux,input-type = <EV_SW>;
71*4882a593Smuzhiyun			gpio-key,wakeup;
72*4882a593Smuzhiyun		};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun		volume_down {
75*4882a593Smuzhiyun			label = "Volume_down";
76*4882a593Smuzhiyun			gpios = <&pio 123 GPIO_ACTIVE_LOW>;
77*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
78*4882a593Smuzhiyun		};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun		volume_up {
81*4882a593Smuzhiyun			label = "Volume_up";
82*4882a593Smuzhiyun			gpios = <&pio 124 GPIO_ACTIVE_LOW>;
83*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
84*4882a593Smuzhiyun		};
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	panel: panel {
88*4882a593Smuzhiyun		compatible = "lg,lp120up1";
89*4882a593Smuzhiyun		power-supply = <&panel_fixed_3v3>;
90*4882a593Smuzhiyun		ddc-i2c-bus = <&i2c0>;
91*4882a593Smuzhiyun		backlight = <&backlight>;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun		port {
94*4882a593Smuzhiyun			panel_in: endpoint {
95*4882a593Smuzhiyun				remote-endpoint = <&ps8640_out>;
96*4882a593Smuzhiyun			};
97*4882a593Smuzhiyun		};
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	panel_fixed_3v3: regulator1 {
101*4882a593Smuzhiyun		compatible = "regulator-fixed";
102*4882a593Smuzhiyun		regulator-name = "PANEL_3V3";
103*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
104*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
105*4882a593Smuzhiyun		enable-active-high;
106*4882a593Smuzhiyun		gpio = <&pio 41 GPIO_ACTIVE_HIGH>;
107*4882a593Smuzhiyun		pinctrl-names = "default";
108*4882a593Smuzhiyun		pinctrl-0 = <&panel_fixed_pins>;
109*4882a593Smuzhiyun	};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun	ps8640_fixed_1v2: regulator2 {
112*4882a593Smuzhiyun		compatible = "regulator-fixed";
113*4882a593Smuzhiyun		regulator-name = "PS8640_1V2";
114*4882a593Smuzhiyun		regulator-min-microvolt = <1200000>;
115*4882a593Smuzhiyun		regulator-max-microvolt = <1200000>;
116*4882a593Smuzhiyun		regulator-enable-ramp-delay = <2000>;
117*4882a593Smuzhiyun		enable-active-high;
118*4882a593Smuzhiyun		regulator-boot-on;
119*4882a593Smuzhiyun		gpio = <&pio 30 GPIO_ACTIVE_HIGH>;
120*4882a593Smuzhiyun		pinctrl-names = "default";
121*4882a593Smuzhiyun		pinctrl-0 = <&ps8640_fixed_pins>;
122*4882a593Smuzhiyun	};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun	sdio_fixed_3v3: fixedregulator0 {
125*4882a593Smuzhiyun		compatible = "regulator-fixed";
126*4882a593Smuzhiyun		regulator-name = "3V3";
127*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
128*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
129*4882a593Smuzhiyun		gpio = <&pio 85 GPIO_ACTIVE_HIGH>;
130*4882a593Smuzhiyun		pinctrl-names = "default";
131*4882a593Smuzhiyun		pinctrl-0 = <&sdio_fixed_3v3_pins>;
132*4882a593Smuzhiyun	};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun	sound: sound {
135*4882a593Smuzhiyun		compatible = "mediatek,mt8173-rt5650";
136*4882a593Smuzhiyun		mediatek,audio-codec = <&rt5650 &hdmi0>;
137*4882a593Smuzhiyun		mediatek,platform = <&afe>;
138*4882a593Smuzhiyun		pinctrl-names = "default";
139*4882a593Smuzhiyun		pinctrl-0 = <&aud_i2s2>;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun		mediatek,mclk = <1>;
142*4882a593Smuzhiyun		codec-capture {
143*4882a593Smuzhiyun			sound-dai = <&rt5650 1>;
144*4882a593Smuzhiyun		};
145*4882a593Smuzhiyun	};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun	hdmicon: connector {
148*4882a593Smuzhiyun		compatible = "hdmi-connector";
149*4882a593Smuzhiyun		label = "hdmi";
150*4882a593Smuzhiyun		type = "a";
151*4882a593Smuzhiyun		ddc-i2c-bus = <&hdmiddc0>;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun		port {
154*4882a593Smuzhiyun			hdmi_connector_in: endpoint {
155*4882a593Smuzhiyun				remote-endpoint = <&hdmi0_out>;
156*4882a593Smuzhiyun			};
157*4882a593Smuzhiyun		};
158*4882a593Smuzhiyun	};
159*4882a593Smuzhiyun};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun&cec {
162*4882a593Smuzhiyun	status = "okay";
163*4882a593Smuzhiyun};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun&cpu0 {
166*4882a593Smuzhiyun	proc-supply = <&mt6397_vpca15_reg>;
167*4882a593Smuzhiyun};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun&cpu1 {
170*4882a593Smuzhiyun	proc-supply = <&mt6397_vpca15_reg>;
171*4882a593Smuzhiyun};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun&cpu2 {
174*4882a593Smuzhiyun	proc-supply = <&da9211_vcpu_reg>;
175*4882a593Smuzhiyun	sram-supply = <&mt6397_vsramca7_reg>;
176*4882a593Smuzhiyun};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun&cpu3 {
179*4882a593Smuzhiyun	proc-supply = <&da9211_vcpu_reg>;
180*4882a593Smuzhiyun	sram-supply = <&mt6397_vsramca7_reg>;
181*4882a593Smuzhiyun};
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun&cpu_thermal {
184*4882a593Smuzhiyun	sustainable-power = <4500>; /* milliwatts */
185*4882a593Smuzhiyun	trips {
186*4882a593Smuzhiyun		threshold: trip-point0 {
187*4882a593Smuzhiyun			temperature = <60000>;
188*4882a593Smuzhiyun		};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun		target: trip-point1 {
191*4882a593Smuzhiyun			temperature = <65000>;
192*4882a593Smuzhiyun		};
193*4882a593Smuzhiyun	};
194*4882a593Smuzhiyun};
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun&dsi0 {
197*4882a593Smuzhiyun	status = "okay";
198*4882a593Smuzhiyun	ports {
199*4882a593Smuzhiyun		port {
200*4882a593Smuzhiyun			dsi0_out: endpoint {
201*4882a593Smuzhiyun				remote-endpoint = <&ps8640_in>;
202*4882a593Smuzhiyun			};
203*4882a593Smuzhiyun		};
204*4882a593Smuzhiyun	};
205*4882a593Smuzhiyun};
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun&dpi0 {
208*4882a593Smuzhiyun	status = "okay";
209*4882a593Smuzhiyun};
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun&hdmi0 {
212*4882a593Smuzhiyun	status = "okay";
213*4882a593Smuzhiyun	ports {
214*4882a593Smuzhiyun		port@1 {
215*4882a593Smuzhiyun			reg = <1>;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun			hdmi0_out: endpoint {
218*4882a593Smuzhiyun				remote-endpoint = <&hdmi_connector_in>;
219*4882a593Smuzhiyun			};
220*4882a593Smuzhiyun		};
221*4882a593Smuzhiyun	};
222*4882a593Smuzhiyun};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun&hdmi_phy {
225*4882a593Smuzhiyun	status = "okay";
226*4882a593Smuzhiyun	mediatek,ibias = <0xc>;
227*4882a593Smuzhiyun};
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun&i2c0 {
230*4882a593Smuzhiyun	status = "okay";
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun	rt5650: audio-codec@1a {
233*4882a593Smuzhiyun		compatible = "realtek,rt5650";
234*4882a593Smuzhiyun		reg = <0x1a>;
235*4882a593Smuzhiyun		avdd-supply = <&mt6397_vgp1_reg>;
236*4882a593Smuzhiyun		cpvdd-supply = <&mt6397_vcama_reg>;
237*4882a593Smuzhiyun		interrupt-parent = <&pio>;
238*4882a593Smuzhiyun		interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
239*4882a593Smuzhiyun		pinctrl-names = "default";
240*4882a593Smuzhiyun		pinctrl-0 = <&rt5650_irq>;
241*4882a593Smuzhiyun		#sound-dai-cells = <1>;
242*4882a593Smuzhiyun		realtek,dmic1-data-pin = <2>;
243*4882a593Smuzhiyun		realtek,jd-mode = <2>;
244*4882a593Smuzhiyun	};
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun	ps8640: edp-bridge@8 {
247*4882a593Smuzhiyun		compatible = "parade,ps8640";
248*4882a593Smuzhiyun		reg = <0x8>;
249*4882a593Smuzhiyun		powerdown-gpios = <&pio 127 GPIO_ACTIVE_LOW>;
250*4882a593Smuzhiyun		reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
251*4882a593Smuzhiyun		pinctrl-names = "default";
252*4882a593Smuzhiyun		pinctrl-0 = <&ps8640_pins>;
253*4882a593Smuzhiyun		vdd12-supply = <&ps8640_fixed_1v2>;
254*4882a593Smuzhiyun		vdd33-supply = <&mt6397_vgp2_reg>;
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun		ports {
257*4882a593Smuzhiyun			#address-cells = <1>;
258*4882a593Smuzhiyun			#size-cells = <0>;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun			port@0 {
261*4882a593Smuzhiyun				reg = <0>;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun				ps8640_in: endpoint {
264*4882a593Smuzhiyun					remote-endpoint = <&dsi0_out>;
265*4882a593Smuzhiyun				};
266*4882a593Smuzhiyun			};
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun			port@1 {
269*4882a593Smuzhiyun				reg = <1>;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun				ps8640_out: endpoint {
272*4882a593Smuzhiyun					remote-endpoint = <&panel_in>;
273*4882a593Smuzhiyun				};
274*4882a593Smuzhiyun			};
275*4882a593Smuzhiyun		};
276*4882a593Smuzhiyun	};
277*4882a593Smuzhiyun};
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun&i2c1 {
280*4882a593Smuzhiyun	clock-frequency = <1500000>;
281*4882a593Smuzhiyun	status = "okay";
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun	da9211: da9211@68 {
284*4882a593Smuzhiyun		compatible = "dlg,da9211";
285*4882a593Smuzhiyun		reg = <0x68>;
286*4882a593Smuzhiyun		interrupt-parent = <&pio>;
287*4882a593Smuzhiyun		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun		regulators {
290*4882a593Smuzhiyun			da9211_vcpu_reg: BUCKA {
291*4882a593Smuzhiyun				regulator-name = "VBUCKA";
292*4882a593Smuzhiyun				regulator-min-microvolt = < 700000>;
293*4882a593Smuzhiyun				regulator-max-microvolt = <1310000>;
294*4882a593Smuzhiyun				regulator-min-microamp  = <2000000>;
295*4882a593Smuzhiyun				regulator-max-microamp  = <4400000>;
296*4882a593Smuzhiyun				regulator-ramp-delay = <10000>;
297*4882a593Smuzhiyun				regulator-always-on;
298*4882a593Smuzhiyun				regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC
299*4882a593Smuzhiyun							   DA9211_BUCK_MODE_AUTO>;
300*4882a593Smuzhiyun			};
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun			da9211_vgpu_reg: BUCKB {
303*4882a593Smuzhiyun				regulator-name = "VBUCKB";
304*4882a593Smuzhiyun				regulator-min-microvolt = < 700000>;
305*4882a593Smuzhiyun				regulator-max-microvolt = <1310000>;
306*4882a593Smuzhiyun				regulator-min-microamp  = <2000000>;
307*4882a593Smuzhiyun				regulator-max-microamp  = <3000000>;
308*4882a593Smuzhiyun				regulator-ramp-delay = <10000>;
309*4882a593Smuzhiyun			};
310*4882a593Smuzhiyun		};
311*4882a593Smuzhiyun	};
312*4882a593Smuzhiyun};
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun&i2c2 {
315*4882a593Smuzhiyun	status = "okay";
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun	tpm: tpm@20 {
318*4882a593Smuzhiyun		compatible = "infineon,slb9645tt";
319*4882a593Smuzhiyun		reg = <0x20>;
320*4882a593Smuzhiyun		powered-while-suspended;
321*4882a593Smuzhiyun	};
322*4882a593Smuzhiyun};
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun&i2c3 {
325*4882a593Smuzhiyun	clock-frequency = <400000>;
326*4882a593Smuzhiyun	status = "okay";
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun	touchscreen: touchscreen@10 {
329*4882a593Smuzhiyun		compatible = "elan,ekth3500";
330*4882a593Smuzhiyun		reg = <0x10>;
331*4882a593Smuzhiyun		interrupt-parent = <&pio>;
332*4882a593Smuzhiyun		interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
333*4882a593Smuzhiyun	};
334*4882a593Smuzhiyun};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun&i2c4 {
337*4882a593Smuzhiyun	clock-frequency = <400000>;
338*4882a593Smuzhiyun	status = "okay";
339*4882a593Smuzhiyun	pinctrl-names = "default";
340*4882a593Smuzhiyun	pinctrl-0 = <&trackpad_irq>;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun	trackpad: trackpad@15 {
343*4882a593Smuzhiyun		compatible = "elan,ekth3000";
344*4882a593Smuzhiyun		interrupt-parent = <&pio>;
345*4882a593Smuzhiyun		interrupts = <117 IRQ_TYPE_LEVEL_LOW>;
346*4882a593Smuzhiyun		reg = <0x15>;
347*4882a593Smuzhiyun		vcc-supply = <&mt6397_vgp6_reg>;
348*4882a593Smuzhiyun		wakeup-source;
349*4882a593Smuzhiyun	};
350*4882a593Smuzhiyun};
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun&mipi_tx0 {
353*4882a593Smuzhiyun	status = "okay";
354*4882a593Smuzhiyun};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun&mmc0 {
357*4882a593Smuzhiyun	status = "okay";
358*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
359*4882a593Smuzhiyun	pinctrl-0 = <&mmc0_pins_default>;
360*4882a593Smuzhiyun	pinctrl-1 = <&mmc0_pins_uhs>;
361*4882a593Smuzhiyun	bus-width = <8>;
362*4882a593Smuzhiyun	max-frequency = <200000000>;
363*4882a593Smuzhiyun	cap-mmc-highspeed;
364*4882a593Smuzhiyun	mmc-hs200-1_8v;
365*4882a593Smuzhiyun	mmc-hs400-1_8v;
366*4882a593Smuzhiyun	cap-mmc-hw-reset;
367*4882a593Smuzhiyun	hs400-ds-delay = <0x14015>;
368*4882a593Smuzhiyun	mediatek,hs200-cmd-int-delay=<30>;
369*4882a593Smuzhiyun	mediatek,hs400-cmd-int-delay=<14>;
370*4882a593Smuzhiyun	mediatek,hs400-cmd-resp-sel-rising;
371*4882a593Smuzhiyun	vmmc-supply = <&mt6397_vemc_3v3_reg>;
372*4882a593Smuzhiyun	vqmmc-supply = <&mt6397_vio18_reg>;
373*4882a593Smuzhiyun	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
374*4882a593Smuzhiyun	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
375*4882a593Smuzhiyun	non-removable;
376*4882a593Smuzhiyun};
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun&mmc1 {
379*4882a593Smuzhiyun	status = "okay";
380*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
381*4882a593Smuzhiyun	pinctrl-0 = <&mmc1_pins_default>;
382*4882a593Smuzhiyun	pinctrl-1 = <&mmc1_pins_uhs>;
383*4882a593Smuzhiyun	bus-width = <4>;
384*4882a593Smuzhiyun	max-frequency = <200000000>;
385*4882a593Smuzhiyun	cap-sd-highspeed;
386*4882a593Smuzhiyun	sd-uhs-sdr50;
387*4882a593Smuzhiyun	sd-uhs-sdr104;
388*4882a593Smuzhiyun	cd-gpios = <&pio 1 GPIO_ACTIVE_LOW>;
389*4882a593Smuzhiyun	vmmc-supply = <&mt6397_vmch_reg>;
390*4882a593Smuzhiyun	vqmmc-supply = <&mt6397_vmc_reg>;
391*4882a593Smuzhiyun};
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun&mmc3 {
394*4882a593Smuzhiyun	status = "okay";
395*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
396*4882a593Smuzhiyun	pinctrl-0 = <&mmc3_pins_default>;
397*4882a593Smuzhiyun	pinctrl-1 = <&mmc3_pins_uhs>;
398*4882a593Smuzhiyun	bus-width = <4>;
399*4882a593Smuzhiyun	max-frequency = <200000000>;
400*4882a593Smuzhiyun	cap-sd-highspeed;
401*4882a593Smuzhiyun	sd-uhs-sdr50;
402*4882a593Smuzhiyun	sd-uhs-sdr104;
403*4882a593Smuzhiyun	keep-power-in-suspend;
404*4882a593Smuzhiyun	enable-sdio-wakeup;
405*4882a593Smuzhiyun	cap-sdio-irq;
406*4882a593Smuzhiyun	vmmc-supply = <&sdio_fixed_3v3>;
407*4882a593Smuzhiyun	vqmmc-supply = <&mt6397_vgp3_reg>;
408*4882a593Smuzhiyun	non-removable;
409*4882a593Smuzhiyun	cap-power-off-card;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun	#address-cells = <1>;
412*4882a593Smuzhiyun	#size-cells = <0>;
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun	btmrvl: btmrvl@2 {
415*4882a593Smuzhiyun		compatible = "marvell,sd8897-bt";
416*4882a593Smuzhiyun		reg = <2>;
417*4882a593Smuzhiyun		interrupt-parent = <&pio>;
418*4882a593Smuzhiyun		interrupts = <119 IRQ_TYPE_LEVEL_LOW>;
419*4882a593Smuzhiyun		marvell,wakeup-pin = /bits/ 16 <0x0d>;
420*4882a593Smuzhiyun		marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
421*4882a593Smuzhiyun	};
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun	mwifiex: mwifiex@1 {
424*4882a593Smuzhiyun		compatible = "marvell,sd8897";
425*4882a593Smuzhiyun		reg = <1>;
426*4882a593Smuzhiyun		interrupt-parent = <&pio>;
427*4882a593Smuzhiyun		interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
428*4882a593Smuzhiyun		marvell,wakeup-pin = <3>;
429*4882a593Smuzhiyun	};
430*4882a593Smuzhiyun};
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun&nor_flash {
433*4882a593Smuzhiyun	status = "okay";
434*4882a593Smuzhiyun	pinctrl-names = "default";
435*4882a593Smuzhiyun	pinctrl-0 = <&nor_gpio1_pins>;
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun	flash@0 {
438*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
439*4882a593Smuzhiyun		reg = <0>;
440*4882a593Smuzhiyun		spi-max-frequency = <50000000>;
441*4882a593Smuzhiyun	};
442*4882a593Smuzhiyun};
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun&pio {
445*4882a593Smuzhiyun	gpio-line-names = "EC_INT_1V8",
446*4882a593Smuzhiyun			  "SD_CD_L",
447*4882a593Smuzhiyun			  "ALC5514_IRQ",
448*4882a593Smuzhiyun			  "ALC5650_IRQ",
449*4882a593Smuzhiyun			  /*
450*4882a593Smuzhiyun			   * AP_FLASH_WP_L is crossystem ABI. Schematics
451*4882a593Smuzhiyun			   * call it SFWP_B.
452*4882a593Smuzhiyun			   */
453*4882a593Smuzhiyun			  "AP_FLASH_WP_L",
454*4882a593Smuzhiyun			  "SFIN",
455*4882a593Smuzhiyun			  "SFCS0",
456*4882a593Smuzhiyun			  "SFHOLD",
457*4882a593Smuzhiyun			  "SFOUT",
458*4882a593Smuzhiyun			  "SFCK",
459*4882a593Smuzhiyun			  "WRAP_EVENT_S_EINT10",
460*4882a593Smuzhiyun			  "PMU_INT",
461*4882a593Smuzhiyun			  "I2S2_WS_ALC5650",
462*4882a593Smuzhiyun			  "I2S2_BCK_ALC5650",
463*4882a593Smuzhiyun			  "PWR_BTN_1V8",
464*4882a593Smuzhiyun			  "DA9212_IRQ",
465*4882a593Smuzhiyun			  "IDDIG",
466*4882a593Smuzhiyun			  "WATCHDOG",
467*4882a593Smuzhiyun			  "CEC",
468*4882a593Smuzhiyun			  "HDMISCK",
469*4882a593Smuzhiyun			  "HDMISD",
470*4882a593Smuzhiyun			  "HTPLG",
471*4882a593Smuzhiyun			  "MSDC3_DAT0",
472*4882a593Smuzhiyun			  "MSDC3_DAT1",
473*4882a593Smuzhiyun			  "MSDC3_DAT2",
474*4882a593Smuzhiyun			  "MSDC3_DAT3",
475*4882a593Smuzhiyun			  "MSDC3_CLK",
476*4882a593Smuzhiyun			  "MSDC3_CMD",
477*4882a593Smuzhiyun			  "USB_C0_OC_FLAGB",
478*4882a593Smuzhiyun			  "USBA_OC1_L",
479*4882a593Smuzhiyun			  "PS8640_1V2_ENABLE",
480*4882a593Smuzhiyun			  "THERM_ALERT_N",
481*4882a593Smuzhiyun			  "PANEL_LCD_POWER_EN",
482*4882a593Smuzhiyun			  "ANX7688_CHIP_PD_C",
483*4882a593Smuzhiyun			  "EC_IN_RW_1V8",
484*4882a593Smuzhiyun			  "ANX7688_1V_EN_C",
485*4882a593Smuzhiyun			  "USB_DP_HPD_C",
486*4882a593Smuzhiyun			  "TPM_DAVINT_N",
487*4882a593Smuzhiyun			  "MARVELL8897_IRQ",
488*4882a593Smuzhiyun			  "EN_USB_A0_PWR",
489*4882a593Smuzhiyun			  "USBA_A0_OC_L",
490*4882a593Smuzhiyun			  "EN_PP3300_DX_EDP",
491*4882a593Smuzhiyun			  "",
492*4882a593Smuzhiyun			  "SOC_I2C2_1V8_SDA_400K",
493*4882a593Smuzhiyun			  "SOC_I2C2_1V8_SCL_400K",
494*4882a593Smuzhiyun			  "SOC_I2C0_1V8_SDA_400K",
495*4882a593Smuzhiyun			  "SOC_I2C0_1V8_SCL_400K",
496*4882a593Smuzhiyun			  "EMMC_ID1",
497*4882a593Smuzhiyun			  "EMMC_ID0",
498*4882a593Smuzhiyun			  "MEM_CONFIG3",
499*4882a593Smuzhiyun			  "EMMC_ID2",
500*4882a593Smuzhiyun			  "MEM_CONFIG1",
501*4882a593Smuzhiyun			  "MEM_CONFIG2",
502*4882a593Smuzhiyun			  "BRD_ID2",
503*4882a593Smuzhiyun			  "MEM_CONFIG0",
504*4882a593Smuzhiyun			  "BRD_ID0",
505*4882a593Smuzhiyun			  "BRD_ID1",
506*4882a593Smuzhiyun			  "EMMC_DAT0",
507*4882a593Smuzhiyun			  "EMMC_DAT1",
508*4882a593Smuzhiyun			  "EMMC_DAT2",
509*4882a593Smuzhiyun			  "EMMC_DAT3",
510*4882a593Smuzhiyun			  "EMMC_DAT4",
511*4882a593Smuzhiyun			  "EMMC_DAT5",
512*4882a593Smuzhiyun			  "EMMC_DAT6",
513*4882a593Smuzhiyun			  "EMMC_DAT7",
514*4882a593Smuzhiyun			  "EMMC_CLK",
515*4882a593Smuzhiyun			  "EMMC_CMD",
516*4882a593Smuzhiyun			  "EMMC_RCLK",
517*4882a593Smuzhiyun			  "PLT_RST_L",
518*4882a593Smuzhiyun			  "LID_OPEN_1V8_L",
519*4882a593Smuzhiyun			  "AUDIO_SPI_MISO_R",
520*4882a593Smuzhiyun			  "",
521*4882a593Smuzhiyun			  "AC_OK_1V8",
522*4882a593Smuzhiyun			  "SD_DATA0",
523*4882a593Smuzhiyun			  "SD_DATA1",
524*4882a593Smuzhiyun			  "SD_DATA2",
525*4882a593Smuzhiyun			  "SD_DATA3",
526*4882a593Smuzhiyun			  "SD_CLK",
527*4882a593Smuzhiyun			  "SD_CMD",
528*4882a593Smuzhiyun			  "PWRAP_SPI0_MI",
529*4882a593Smuzhiyun			  "PWRAP_SPI0_MO",
530*4882a593Smuzhiyun			  "PWRAP_SPI0_CK",
531*4882a593Smuzhiyun			  "PWRAP_SPI0_CSN",
532*4882a593Smuzhiyun			  "",
533*4882a593Smuzhiyun			  "",
534*4882a593Smuzhiyun			  "WIFI_PDN",
535*4882a593Smuzhiyun			  "RTC32K_1V8",
536*4882a593Smuzhiyun			  "DISP_PWM0",
537*4882a593Smuzhiyun			  "TOUCHSCREEN_INT_L",
538*4882a593Smuzhiyun			  "",
539*4882a593Smuzhiyun			  "SRCLKENA0",
540*4882a593Smuzhiyun			  "SRCLKENA1",
541*4882a593Smuzhiyun			  "PS8640_MODE_CONF",
542*4882a593Smuzhiyun			  "TOUCHSCREEN_RESET_R",
543*4882a593Smuzhiyun			  "PLATFORM_PROCHOT_L",
544*4882a593Smuzhiyun			  "PANEL_POWER_EN",
545*4882a593Smuzhiyun			  "REC_MODE_L",
546*4882a593Smuzhiyun			  "EC_FW_UPDATE_L",
547*4882a593Smuzhiyun			  "ACCEL2_INT_L",
548*4882a593Smuzhiyun			  "HDMI_DP_INT",
549*4882a593Smuzhiyun			  "ACCELGYRO3_INT_L",
550*4882a593Smuzhiyun			  "ACCELGYRO4_INT_L",
551*4882a593Smuzhiyun			  "SPI_EC_CLK",
552*4882a593Smuzhiyun			  "SPI_EC_MI",
553*4882a593Smuzhiyun			  "SPI_EC_MO",
554*4882a593Smuzhiyun			  "SPI_EC_CSN",
555*4882a593Smuzhiyun			  "SOC_I2C3_1V8_SDA_400K",
556*4882a593Smuzhiyun			  "SOC_I2C3_1V8_SCL_400K",
557*4882a593Smuzhiyun			  "",
558*4882a593Smuzhiyun			  "",
559*4882a593Smuzhiyun			  "",
560*4882a593Smuzhiyun			  "",
561*4882a593Smuzhiyun			  "",
562*4882a593Smuzhiyun			  "",
563*4882a593Smuzhiyun			  "",
564*4882a593Smuzhiyun			  "PS8640_SYSRSTN_1V8",
565*4882a593Smuzhiyun			  "APIN_MAX98090_DOUT2",
566*4882a593Smuzhiyun			  "TP_INT_1V8_L_R",
567*4882a593Smuzhiyun			  "RST_USB_HUB_R",
568*4882a593Smuzhiyun			  "BT_WAKE_L",
569*4882a593Smuzhiyun			  "ACCEL1_INT_L",
570*4882a593Smuzhiyun			  "TABLET_MODE_L",
571*4882a593Smuzhiyun			  "",
572*4882a593Smuzhiyun			  "V_UP_IN_L_R",
573*4882a593Smuzhiyun			  "V_DOWN_IN_L_R",
574*4882a593Smuzhiyun			  "SOC_I2C1_1V8_SDA_1M",
575*4882a593Smuzhiyun			  "SOC_I2C1_1V8_SCL_1M",
576*4882a593Smuzhiyun			  "PS8640_PDN_1V8",
577*4882a593Smuzhiyun			  "MAX98090_LRCLK",
578*4882a593Smuzhiyun			  "MAX98090_BCLK",
579*4882a593Smuzhiyun			  "MAX98090_MCLK",
580*4882a593Smuzhiyun			  "APOUT_MAX98090_DIN",
581*4882a593Smuzhiyun			  "APIN_MAX98090_DOUT",
582*4882a593Smuzhiyun			  "SOC_I2C4_1V8_SDA_400K",
583*4882a593Smuzhiyun			  "SOC_I2C4_1V8_SCL_400K";
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun	aud_i2s2: aud_i2s2 {
586*4882a593Smuzhiyun		pins1 {
587*4882a593Smuzhiyun			pinmux = <MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS>,
588*4882a593Smuzhiyun				 <MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK>,
589*4882a593Smuzhiyun				 <MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK>,
590*4882a593Smuzhiyun				 <MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1>,
591*4882a593Smuzhiyun				 <MT8173_PIN_12_EINT12__FUNC_I2S2_WS>,
592*4882a593Smuzhiyun				 <MT8173_PIN_13_EINT13__FUNC_I2S2_BCK>,
593*4882a593Smuzhiyun				 <MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2>;
594*4882a593Smuzhiyun			bias-pull-down;
595*4882a593Smuzhiyun		};
596*4882a593Smuzhiyun	};
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun	bl_fixed_pins: bl_fixed_pins {
599*4882a593Smuzhiyun		pins1 {
600*4882a593Smuzhiyun			pinmux = <MT8173_PIN_32_UTXD2__FUNC_GPIO32>;
601*4882a593Smuzhiyun			output-low;
602*4882a593Smuzhiyun		};
603*4882a593Smuzhiyun	};
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun	bt_wake_pins: bt_wake_pins {
606*4882a593Smuzhiyun		pins1 {
607*4882a593Smuzhiyun			pinmux = <MT8173_PIN_119_KPROW0__FUNC_GPIO119>;
608*4882a593Smuzhiyun			bias-pull-up;
609*4882a593Smuzhiyun		};
610*4882a593Smuzhiyun	};
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun	disp_pwm0_pins: disp_pwm0_pins {
613*4882a593Smuzhiyun		pins1 {
614*4882a593Smuzhiyun			pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
615*4882a593Smuzhiyun			output-low;
616*4882a593Smuzhiyun		};
617*4882a593Smuzhiyun	};
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun	gpio_keys_pins: gpio_keys_pins {
620*4882a593Smuzhiyun		volume_pins {
621*4882a593Smuzhiyun			pinmux = <MT8173_PIN_123_KPCOL1__FUNC_GPIO123>,
622*4882a593Smuzhiyun				 <MT8173_PIN_124_KPCOL2__FUNC_GPIO124>;
623*4882a593Smuzhiyun			bias-pull-up;
624*4882a593Smuzhiyun		};
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun		tablet_mode_pins {
627*4882a593Smuzhiyun			pinmux = <MT8173_PIN_121_KPROW2__FUNC_GPIO121>;
628*4882a593Smuzhiyun			bias-pull-up;
629*4882a593Smuzhiyun		};
630*4882a593Smuzhiyun	};
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun	hdmi_mux_pins: hdmi_mux_pins {
633*4882a593Smuzhiyun		pins1 {
634*4882a593Smuzhiyun			pinmux = <MT8173_PIN_36_DAISYNC__FUNC_GPIO36>;
635*4882a593Smuzhiyun		};
636*4882a593Smuzhiyun	};
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun	i2c1_pins_a: i2c1 {
639*4882a593Smuzhiyun		da9211_pins {
640*4882a593Smuzhiyun			pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>;
641*4882a593Smuzhiyun			bias-pull-up;
642*4882a593Smuzhiyun		};
643*4882a593Smuzhiyun	};
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun	mmc0_pins_default: mmc0default {
646*4882a593Smuzhiyun		pins_cmd_dat {
647*4882a593Smuzhiyun			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
648*4882a593Smuzhiyun				 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
649*4882a593Smuzhiyun				 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
650*4882a593Smuzhiyun				 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
651*4882a593Smuzhiyun				 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
652*4882a593Smuzhiyun				 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
653*4882a593Smuzhiyun				 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
654*4882a593Smuzhiyun				 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
655*4882a593Smuzhiyun				 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
656*4882a593Smuzhiyun			bias-pull-up;
657*4882a593Smuzhiyun		};
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun		pins_clk {
660*4882a593Smuzhiyun			pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
661*4882a593Smuzhiyun			bias-pull-down;
662*4882a593Smuzhiyun		};
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun		pins_rst {
665*4882a593Smuzhiyun			pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
666*4882a593Smuzhiyun			bias-pull-up;
667*4882a593Smuzhiyun		};
668*4882a593Smuzhiyun	};
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun	mmc1_pins_default: mmc1default {
671*4882a593Smuzhiyun		pins_cmd_dat {
672*4882a593Smuzhiyun			pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
673*4882a593Smuzhiyun				 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
674*4882a593Smuzhiyun				 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
675*4882a593Smuzhiyun				 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
676*4882a593Smuzhiyun				 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
677*4882a593Smuzhiyun			input-enable;
678*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_4mA>;
679*4882a593Smuzhiyun			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
680*4882a593Smuzhiyun		};
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun		pins_clk {
683*4882a593Smuzhiyun			pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
684*4882a593Smuzhiyun			bias-pull-down;
685*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_4mA>;
686*4882a593Smuzhiyun		};
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun		pins_insert {
689*4882a593Smuzhiyun			pinmux = <MT8173_PIN_1_EINT1__FUNC_GPIO1>;
690*4882a593Smuzhiyun			bias-pull-up;
691*4882a593Smuzhiyun		};
692*4882a593Smuzhiyun	};
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun	mmc3_pins_default: mmc3default {
695*4882a593Smuzhiyun		pins_dat {
696*4882a593Smuzhiyun			pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>,
697*4882a593Smuzhiyun				 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>,
698*4882a593Smuzhiyun				 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>,
699*4882a593Smuzhiyun				 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>;
700*4882a593Smuzhiyun			input-enable;
701*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_8mA>;
702*4882a593Smuzhiyun			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
703*4882a593Smuzhiyun		};
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun		pins_cmd {
706*4882a593Smuzhiyun			pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>;
707*4882a593Smuzhiyun			input-enable;
708*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_8mA>;
709*4882a593Smuzhiyun			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
710*4882a593Smuzhiyun		};
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun		pins_clk {
713*4882a593Smuzhiyun			pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>;
714*4882a593Smuzhiyun			bias-pull-down;
715*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_8mA>;
716*4882a593Smuzhiyun		};
717*4882a593Smuzhiyun	};
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun	mmc0_pins_uhs: mmc0 {
720*4882a593Smuzhiyun		pins_cmd_dat {
721*4882a593Smuzhiyun			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
722*4882a593Smuzhiyun				 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
723*4882a593Smuzhiyun				 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
724*4882a593Smuzhiyun				 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
725*4882a593Smuzhiyun				 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
726*4882a593Smuzhiyun				 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
727*4882a593Smuzhiyun				 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
728*4882a593Smuzhiyun				 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
729*4882a593Smuzhiyun				 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
730*4882a593Smuzhiyun			input-enable;
731*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_6mA>;
732*4882a593Smuzhiyun			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
733*4882a593Smuzhiyun		};
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun		pins_clk {
736*4882a593Smuzhiyun			pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
737*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_6mA>;
738*4882a593Smuzhiyun			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
739*4882a593Smuzhiyun		};
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun		pins_ds {
742*4882a593Smuzhiyun			pinmux = <MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL>;
743*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_10mA>;
744*4882a593Smuzhiyun			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
745*4882a593Smuzhiyun		};
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun		pins_rst {
748*4882a593Smuzhiyun			pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
749*4882a593Smuzhiyun			bias-pull-up;
750*4882a593Smuzhiyun		};
751*4882a593Smuzhiyun	};
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun	mmc1_pins_uhs: mmc1 {
754*4882a593Smuzhiyun		pins_cmd_dat {
755*4882a593Smuzhiyun			pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
756*4882a593Smuzhiyun				 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
757*4882a593Smuzhiyun				 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
758*4882a593Smuzhiyun				 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
759*4882a593Smuzhiyun				 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
760*4882a593Smuzhiyun			input-enable;
761*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_6mA>;
762*4882a593Smuzhiyun			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
763*4882a593Smuzhiyun		};
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun		pins_clk {
766*4882a593Smuzhiyun			pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
767*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_8mA>;
768*4882a593Smuzhiyun			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
769*4882a593Smuzhiyun		};
770*4882a593Smuzhiyun	};
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun	mmc3_pins_uhs: mmc3 {
773*4882a593Smuzhiyun		pins_dat {
774*4882a593Smuzhiyun			pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>,
775*4882a593Smuzhiyun				 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>,
776*4882a593Smuzhiyun				 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>,
777*4882a593Smuzhiyun				 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>;
778*4882a593Smuzhiyun			input-enable;
779*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_8mA>;
780*4882a593Smuzhiyun			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
781*4882a593Smuzhiyun		};
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun		pins_cmd {
784*4882a593Smuzhiyun			pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>;
785*4882a593Smuzhiyun			input-enable;
786*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_8mA>;
787*4882a593Smuzhiyun			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
788*4882a593Smuzhiyun		};
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun		pins_clk {
791*4882a593Smuzhiyun			pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>;
792*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_8mA>;
793*4882a593Smuzhiyun			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
794*4882a593Smuzhiyun		};
795*4882a593Smuzhiyun	};
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun	nor_gpio1_pins: nor {
798*4882a593Smuzhiyun		pins1 {
799*4882a593Smuzhiyun			pinmux = <MT8173_PIN_6_EINT6__FUNC_SFCS0>,
800*4882a593Smuzhiyun				 <MT8173_PIN_7_EINT7__FUNC_SFHOLD>,
801*4882a593Smuzhiyun				 <MT8173_PIN_8_EINT8__FUNC_SFIN>;
802*4882a593Smuzhiyun			input-enable;
803*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_4mA>;
804*4882a593Smuzhiyun			bias-pull-up;
805*4882a593Smuzhiyun		};
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun		pins2 {
808*4882a593Smuzhiyun			pinmux = <MT8173_PIN_5_EINT5__FUNC_SFOUT>;
809*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_4mA>;
810*4882a593Smuzhiyun			bias-pull-up;
811*4882a593Smuzhiyun		};
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun		pins_clk {
814*4882a593Smuzhiyun			pinmux = <MT8173_PIN_9_EINT9__FUNC_SFCK>;
815*4882a593Smuzhiyun			input-enable;
816*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_4mA>;
817*4882a593Smuzhiyun			bias-pull-up;
818*4882a593Smuzhiyun		};
819*4882a593Smuzhiyun	};
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun	panel_fixed_pins: panel_fixed_pins {
822*4882a593Smuzhiyun		pins1 {
823*4882a593Smuzhiyun			pinmux = <MT8173_PIN_41_CMMCLK__FUNC_GPIO41>;
824*4882a593Smuzhiyun		};
825*4882a593Smuzhiyun	};
826*4882a593Smuzhiyun
827*4882a593Smuzhiyun	ps8640_pins: ps8640_pins {
828*4882a593Smuzhiyun		pins1 {
829*4882a593Smuzhiyun			pinmux = <MT8173_PIN_92_PCM_CLK__FUNC_GPIO92>,
830*4882a593Smuzhiyun				 <MT8173_PIN_115_URTS0__FUNC_GPIO115>,
831*4882a593Smuzhiyun				 <MT8173_PIN_127_LCM_RST__FUNC_GPIO127>;
832*4882a593Smuzhiyun		};
833*4882a593Smuzhiyun	};
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun	ps8640_fixed_pins: ps8640_fixed_pins {
836*4882a593Smuzhiyun		pins1 {
837*4882a593Smuzhiyun			pinmux = <MT8173_PIN_30_URTS2__FUNC_GPIO30>;
838*4882a593Smuzhiyun		};
839*4882a593Smuzhiyun	};
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun	rt5650_irq: rt5650_irq {
842*4882a593Smuzhiyun		pins1 {
843*4882a593Smuzhiyun			pinmux = <MT8173_PIN_3_EINT3__FUNC_GPIO3>;
844*4882a593Smuzhiyun			bias-pull-down;
845*4882a593Smuzhiyun		};
846*4882a593Smuzhiyun	};
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun	sdio_fixed_3v3_pins: sdio_fixed_3v3_pins {
849*4882a593Smuzhiyun		pins1 {
850*4882a593Smuzhiyun			pinmux = <MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85>;
851*4882a593Smuzhiyun			output-low;
852*4882a593Smuzhiyun		};
853*4882a593Smuzhiyun	};
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun	spi_pins_a: spi1 {
856*4882a593Smuzhiyun		pins1 {
857*4882a593Smuzhiyun			pinmux = <MT8173_PIN_0_EINT0__FUNC_GPIO0>;
858*4882a593Smuzhiyun			bias-pull-up;
859*4882a593Smuzhiyun		};
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun		pins_spi {
862*4882a593Smuzhiyun			pinmux = <MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_>,
863*4882a593Smuzhiyun				 <MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_>,
864*4882a593Smuzhiyun				 <MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_>,
865*4882a593Smuzhiyun				 <MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_>;
866*4882a593Smuzhiyun			bias-disable;
867*4882a593Smuzhiyun		};
868*4882a593Smuzhiyun	};
869*4882a593Smuzhiyun
870*4882a593Smuzhiyun	trackpad_irq: trackpad_irq {
871*4882a593Smuzhiyun		pins1 {
872*4882a593Smuzhiyun			pinmux = <MT8173_PIN_117_URXD3__FUNC_GPIO117>;
873*4882a593Smuzhiyun			input-enable;
874*4882a593Smuzhiyun			bias-pull-up;
875*4882a593Smuzhiyun		};
876*4882a593Smuzhiyun	};
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun	usb_pins: usb {
879*4882a593Smuzhiyun		pins1 {
880*4882a593Smuzhiyun			pinmux = <MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101>;
881*4882a593Smuzhiyun			output-high;
882*4882a593Smuzhiyun			bias-disable;
883*4882a593Smuzhiyun		};
884*4882a593Smuzhiyun	};
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun	wifi_wake_pins: wifi_wake_pins {
887*4882a593Smuzhiyun		pins1 {
888*4882a593Smuzhiyun			pinmux = <MT8173_PIN_38_CONN_RST__FUNC_GPIO38>;
889*4882a593Smuzhiyun			bias-pull-up;
890*4882a593Smuzhiyun		};
891*4882a593Smuzhiyun	};
892*4882a593Smuzhiyun};
893*4882a593Smuzhiyun
894*4882a593Smuzhiyun&pwm0 {
895*4882a593Smuzhiyun	status = "okay";
896*4882a593Smuzhiyun};
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun&pwrap {
899*4882a593Smuzhiyun	pmic: mt6397 {
900*4882a593Smuzhiyun		compatible = "mediatek,mt6397";
901*4882a593Smuzhiyun		#address-cells = <1>;
902*4882a593Smuzhiyun		#size-cells = <1>;
903*4882a593Smuzhiyun		interrupt-parent = <&pio>;
904*4882a593Smuzhiyun		interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
905*4882a593Smuzhiyun		interrupt-controller;
906*4882a593Smuzhiyun		#interrupt-cells = <2>;
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun		clock: mt6397clock {
909*4882a593Smuzhiyun			compatible = "mediatek,mt6397-clk";
910*4882a593Smuzhiyun			#clock-cells = <1>;
911*4882a593Smuzhiyun		};
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun		pio6397: pinctrl {
914*4882a593Smuzhiyun			compatible = "mediatek,mt6397-pinctrl";
915*4882a593Smuzhiyun			pins-are-numbered;
916*4882a593Smuzhiyun			gpio-controller;
917*4882a593Smuzhiyun			#gpio-cells = <2>;
918*4882a593Smuzhiyun		};
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun		regulator: mt6397regulator {
921*4882a593Smuzhiyun			compatible = "mediatek,mt6397-regulator";
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun			mt6397_vpca15_reg: buck_vpca15 {
924*4882a593Smuzhiyun				regulator-compatible = "buck_vpca15";
925*4882a593Smuzhiyun				regulator-name = "vpca15";
926*4882a593Smuzhiyun				regulator-min-microvolt = < 700000>;
927*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
928*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
929*4882a593Smuzhiyun				regulator-always-on;
930*4882a593Smuzhiyun				regulator-allowed-modes = <0 1>;
931*4882a593Smuzhiyun			};
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun			mt6397_vpca7_reg: buck_vpca7 {
934*4882a593Smuzhiyun				regulator-compatible = "buck_vpca7";
935*4882a593Smuzhiyun				regulator-name = "vpca7";
936*4882a593Smuzhiyun				regulator-min-microvolt = < 700000>;
937*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
938*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
939*4882a593Smuzhiyun				regulator-enable-ramp-delay = <115>;
940*4882a593Smuzhiyun				regulator-always-on;
941*4882a593Smuzhiyun			};
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun			mt6397_vsramca15_reg: buck_vsramca15 {
944*4882a593Smuzhiyun				regulator-compatible = "buck_vsramca15";
945*4882a593Smuzhiyun				regulator-name = "vsramca15";
946*4882a593Smuzhiyun				regulator-min-microvolt = < 700000>;
947*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
948*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
949*4882a593Smuzhiyun				regulator-always-on;
950*4882a593Smuzhiyun			};
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun			mt6397_vsramca7_reg: buck_vsramca7 {
953*4882a593Smuzhiyun				regulator-compatible = "buck_vsramca7";
954*4882a593Smuzhiyun				regulator-name = "vsramca7";
955*4882a593Smuzhiyun				regulator-min-microvolt = < 700000>;
956*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
957*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
958*4882a593Smuzhiyun				regulator-always-on;
959*4882a593Smuzhiyun			};
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun			mt6397_vcore_reg: buck_vcore {
962*4882a593Smuzhiyun				regulator-compatible = "buck_vcore";
963*4882a593Smuzhiyun				regulator-name = "vcore";
964*4882a593Smuzhiyun				regulator-min-microvolt = < 700000>;
965*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
966*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
967*4882a593Smuzhiyun				regulator-always-on;
968*4882a593Smuzhiyun			};
969*4882a593Smuzhiyun
970*4882a593Smuzhiyun			mt6397_vgpu_reg: buck_vgpu {
971*4882a593Smuzhiyun				regulator-compatible = "buck_vgpu";
972*4882a593Smuzhiyun				regulator-name = "vgpu";
973*4882a593Smuzhiyun				regulator-min-microvolt = < 700000>;
974*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
975*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
976*4882a593Smuzhiyun				regulator-enable-ramp-delay = <115>;
977*4882a593Smuzhiyun			};
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun			mt6397_vdrm_reg: buck_vdrm {
980*4882a593Smuzhiyun				regulator-compatible = "buck_vdrm";
981*4882a593Smuzhiyun				regulator-name = "vdrm";
982*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
983*4882a593Smuzhiyun				regulator-max-microvolt = <1400000>;
984*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
985*4882a593Smuzhiyun				regulator-always-on;
986*4882a593Smuzhiyun			};
987*4882a593Smuzhiyun
988*4882a593Smuzhiyun			mt6397_vio18_reg: buck_vio18 {
989*4882a593Smuzhiyun				regulator-compatible = "buck_vio18";
990*4882a593Smuzhiyun				regulator-name = "vio18";
991*4882a593Smuzhiyun				regulator-min-microvolt = <1620000>;
992*4882a593Smuzhiyun				regulator-max-microvolt = <1980000>;
993*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
994*4882a593Smuzhiyun				regulator-always-on;
995*4882a593Smuzhiyun			};
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun			mt6397_vtcxo_reg: ldo_vtcxo {
998*4882a593Smuzhiyun				regulator-compatible = "ldo_vtcxo";
999*4882a593Smuzhiyun				regulator-name = "vtcxo";
1000*4882a593Smuzhiyun				regulator-always-on;
1001*4882a593Smuzhiyun			};
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun			mt6397_va28_reg: ldo_va28 {
1004*4882a593Smuzhiyun				regulator-compatible = "ldo_va28";
1005*4882a593Smuzhiyun				regulator-name = "va28";
1006*4882a593Smuzhiyun			};
1007*4882a593Smuzhiyun
1008*4882a593Smuzhiyun			mt6397_vcama_reg: ldo_vcama {
1009*4882a593Smuzhiyun				regulator-compatible = "ldo_vcama";
1010*4882a593Smuzhiyun				regulator-name = "vcama";
1011*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
1012*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
1013*4882a593Smuzhiyun				regulator-enable-ramp-delay = <218>;
1014*4882a593Smuzhiyun			};
1015*4882a593Smuzhiyun
1016*4882a593Smuzhiyun			mt6397_vio28_reg: ldo_vio28 {
1017*4882a593Smuzhiyun				regulator-compatible = "ldo_vio28";
1018*4882a593Smuzhiyun				regulator-name = "vio28";
1019*4882a593Smuzhiyun				regulator-always-on;
1020*4882a593Smuzhiyun			};
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun			mt6397_vusb_reg: ldo_vusb {
1023*4882a593Smuzhiyun				regulator-compatible = "ldo_vusb";
1024*4882a593Smuzhiyun				regulator-name = "vusb";
1025*4882a593Smuzhiyun			};
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun			mt6397_vmc_reg: ldo_vmc {
1028*4882a593Smuzhiyun				regulator-compatible = "ldo_vmc";
1029*4882a593Smuzhiyun				regulator-name = "vmc";
1030*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
1031*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
1032*4882a593Smuzhiyun				regulator-enable-ramp-delay = <218>;
1033*4882a593Smuzhiyun			};
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun			mt6397_vmch_reg: ldo_vmch {
1036*4882a593Smuzhiyun				regulator-compatible = "ldo_vmch";
1037*4882a593Smuzhiyun				regulator-name = "vmch";
1038*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
1039*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
1040*4882a593Smuzhiyun				regulator-enable-ramp-delay = <218>;
1041*4882a593Smuzhiyun			};
1042*4882a593Smuzhiyun
1043*4882a593Smuzhiyun			mt6397_vemc_3v3_reg: ldo_vemc3v3 {
1044*4882a593Smuzhiyun				regulator-compatible = "ldo_vemc3v3";
1045*4882a593Smuzhiyun				regulator-name = "vemc_3v3";
1046*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
1047*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
1048*4882a593Smuzhiyun				regulator-enable-ramp-delay = <218>;
1049*4882a593Smuzhiyun			};
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun			mt6397_vgp1_reg: ldo_vgp1 {
1052*4882a593Smuzhiyun				regulator-compatible = "ldo_vgp1";
1053*4882a593Smuzhiyun				regulator-name = "vcamd";
1054*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
1055*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
1056*4882a593Smuzhiyun				regulator-enable-ramp-delay = <240>;
1057*4882a593Smuzhiyun			};
1058*4882a593Smuzhiyun
1059*4882a593Smuzhiyun			mt6397_vgp2_reg: ldo_vgp2 {
1060*4882a593Smuzhiyun				regulator-compatible = "ldo_vgp2";
1061*4882a593Smuzhiyun				regulator-name = "vcamio";
1062*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
1063*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
1064*4882a593Smuzhiyun				regulator-enable-ramp-delay = <218>;
1065*4882a593Smuzhiyun			};
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun			mt6397_vgp3_reg: ldo_vgp3 {
1068*4882a593Smuzhiyun				regulator-compatible = "ldo_vgp3";
1069*4882a593Smuzhiyun				regulator-name = "vcamaf";
1070*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
1071*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
1072*4882a593Smuzhiyun				regulator-enable-ramp-delay = <218>;
1073*4882a593Smuzhiyun			};
1074*4882a593Smuzhiyun
1075*4882a593Smuzhiyun			mt6397_vgp4_reg: ldo_vgp4 {
1076*4882a593Smuzhiyun				regulator-compatible = "ldo_vgp4";
1077*4882a593Smuzhiyun				regulator-name = "vgp4";
1078*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
1079*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
1080*4882a593Smuzhiyun				regulator-enable-ramp-delay = <218>;
1081*4882a593Smuzhiyun			};
1082*4882a593Smuzhiyun
1083*4882a593Smuzhiyun			mt6397_vgp5_reg: ldo_vgp5 {
1084*4882a593Smuzhiyun				regulator-compatible = "ldo_vgp5";
1085*4882a593Smuzhiyun				regulator-name = "vgp5";
1086*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
1087*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
1088*4882a593Smuzhiyun				regulator-enable-ramp-delay = <218>;
1089*4882a593Smuzhiyun			};
1090*4882a593Smuzhiyun
1091*4882a593Smuzhiyun			mt6397_vgp6_reg: ldo_vgp6 {
1092*4882a593Smuzhiyun				regulator-compatible = "ldo_vgp6";
1093*4882a593Smuzhiyun				regulator-name = "vgp6";
1094*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
1095*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
1096*4882a593Smuzhiyun				regulator-enable-ramp-delay = <218>;
1097*4882a593Smuzhiyun				regulator-always-on;
1098*4882a593Smuzhiyun			};
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun			mt6397_vibr_reg: ldo_vibr {
1101*4882a593Smuzhiyun				regulator-compatible = "ldo_vibr";
1102*4882a593Smuzhiyun				regulator-name = "vibr";
1103*4882a593Smuzhiyun				regulator-min-microvolt = <1300000>;
1104*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
1105*4882a593Smuzhiyun				regulator-enable-ramp-delay = <218>;
1106*4882a593Smuzhiyun			};
1107*4882a593Smuzhiyun		};
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun		rtc: mt6397rtc {
1110*4882a593Smuzhiyun			compatible = "mediatek,mt6397-rtc";
1111*4882a593Smuzhiyun		};
1112*4882a593Smuzhiyun
1113*4882a593Smuzhiyun		syscfg_pctl_pmic: syscfg_pctl_pmic@c000 {
1114*4882a593Smuzhiyun			compatible = "mediatek,mt6397-pctl-pmic-syscfg",
1115*4882a593Smuzhiyun				     "syscon";
1116*4882a593Smuzhiyun			reg = <0 0x0000c000 0 0x0108>;
1117*4882a593Smuzhiyun		};
1118*4882a593Smuzhiyun	};
1119*4882a593Smuzhiyun};
1120*4882a593Smuzhiyun
1121*4882a593Smuzhiyun&spi {
1122*4882a593Smuzhiyun	pinctrl-names = "default";
1123*4882a593Smuzhiyun	pinctrl-0 = <&spi_pins_a>;
1124*4882a593Smuzhiyun	mediatek,pad-select = <1>;
1125*4882a593Smuzhiyun	status = "okay";
1126*4882a593Smuzhiyun	/* clients */
1127*4882a593Smuzhiyun	cros_ec: ec@0 {
1128*4882a593Smuzhiyun		compatible = "google,cros-ec-spi";
1129*4882a593Smuzhiyun		reg = <0x0>;
1130*4882a593Smuzhiyun		spi-max-frequency = <12000000>;
1131*4882a593Smuzhiyun		interrupt-parent = <&pio>;
1132*4882a593Smuzhiyun		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
1133*4882a593Smuzhiyun		google,cros-ec-spi-msg-delay = <500>;
1134*4882a593Smuzhiyun
1135*4882a593Smuzhiyun		i2c_tunnel: i2c-tunnel0 {
1136*4882a593Smuzhiyun			compatible = "google,cros-ec-i2c-tunnel";
1137*4882a593Smuzhiyun			google,remote-bus = <0>;
1138*4882a593Smuzhiyun			#address-cells = <1>;
1139*4882a593Smuzhiyun			#size-cells = <0>;
1140*4882a593Smuzhiyun
1141*4882a593Smuzhiyun			battery: sbs-battery@b {
1142*4882a593Smuzhiyun				compatible = "sbs,sbs-battery";
1143*4882a593Smuzhiyun				reg = <0xb>;
1144*4882a593Smuzhiyun				sbs,i2c-retry-count = <2>;
1145*4882a593Smuzhiyun				sbs,poll-retry-count = <1>;
1146*4882a593Smuzhiyun			};
1147*4882a593Smuzhiyun		};
1148*4882a593Smuzhiyun	};
1149*4882a593Smuzhiyun};
1150*4882a593Smuzhiyun
1151*4882a593Smuzhiyun&ssusb {
1152*4882a593Smuzhiyun	dr_mode = "host";
1153*4882a593Smuzhiyun	wakeup-source;
1154*4882a593Smuzhiyun	vusb33-supply = <&mt6397_vusb_reg>;
1155*4882a593Smuzhiyun	status = "okay";
1156*4882a593Smuzhiyun};
1157*4882a593Smuzhiyun
1158*4882a593Smuzhiyun&thermal {
1159*4882a593Smuzhiyun	bank0-supply = <&mt6397_vpca15_reg>;
1160*4882a593Smuzhiyun	bank1-supply = <&da9211_vcpu_reg>;
1161*4882a593Smuzhiyun};
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun&uart0 {
1164*4882a593Smuzhiyun	status = "okay";
1165*4882a593Smuzhiyun};
1166*4882a593Smuzhiyun
1167*4882a593Smuzhiyun&usb_host {
1168*4882a593Smuzhiyun	pinctrl-names = "default";
1169*4882a593Smuzhiyun	pinctrl-0 = <&usb_pins>;
1170*4882a593Smuzhiyun	vusb33-supply = <&mt6397_vusb_reg>;
1171*4882a593Smuzhiyun	status = "okay";
1172*4882a593Smuzhiyun};
1173*4882a593Smuzhiyun
1174*4882a593Smuzhiyun#include <arm/cros-ec-keyboard.dtsi>
1175