Home
last modified time | relevance | path

Searched refs:i (Results 376 – 400 of 613) sorted by relevance

1...<<11121314151617181920>>...25

/rk3399_ARM-atf/drivers/st/ddr/
H A Dstm32mp_ddr.c32 unsigned int i; in stm32mp_ddr_set_reg() local
39 for (i = 0; i < ddr_registers[type].size; i++) { in stm32mp_ddr_set_reg()
40 uintptr_t ptr = base_addr + desc[i].offset; in stm32mp_ddr_set_reg()
42 if (desc[i].par_offset == INVALID_OFFSET) { in stm32mp_ddr_set_reg()
44 ddr_registers[type].name, i); in stm32mp_ddr_set_reg()
48 if (desc[i].qd) { in stm32mp_ddr_set_reg()
53 desc[i].par_offset)); in stm32mp_ddr_set_reg()
56 if (desc[i].qd) { in stm32mp_ddr_set_reg()
/rk3399_ARM-atf/drivers/st/pmic/
H A Dstpmic2.c292 unsigned int i; in voltage_to_index() local
295 for (i = 0U; i < regul->volt_table_size; i++) { in voltage_to_index()
296 if (regul->volt_table[i] == millivolts) { in voltage_to_index()
297 return i; in voltage_to_index()
440 size_t i; in stpmic2_dump_regulators() local
443 for (i = 0U; i < ARRAY_SIZE(regul_table); i++) { in stpmic2_dump_regulators()
447 if (!regul_table[i].volt_cr) { in stpmic2_dump_regulators()
451 stpmic2_regulator_get_voltage(pmic, i, &val); in stpmic2_dump_regulators()
452 stpmic2_regulator_get_state(pmic, i, &state); in stpmic2_dump_regulators()
454 name = regul_table[i].name; in stpmic2_dump_regulators()
/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dzynqmp_pm_svc_main.c65 int i; in trigger_wdt_restart() local
67 for (i = 0; i < 4; i++) { in trigger_wdt_restart()
68 pm_get_node_status(NODE_APU_0 + i, core_status, SECURE); in trigger_wdt_restart()
71 target_cpu_list |= (1 << i); in trigger_wdt_restart()
81 for (i = PLATFORM_CORE_COUNT - 1; i >= 0; i--) { in trigger_wdt_restart()
82 if (target_cpu_list & (1 << i)) { in trigger_wdt_restart()
84 plat_ic_raise_el3_sgi(ARM_IRQ_SEC_SGI_7, i); in trigger_wdt_restart()
150 int i; in zynqmp_sgi7_irq() local
159 for (i = 0; i < 4; i++) { in zynqmp_sgi7_irq()
160 mmio_write_32(BASE_GICD_BASE + GICD_CPENDSGIR + 4 * i, in zynqmp_sgi7_irq()
H A Dpm_api_clock.c2408 unsigned int i; in pm_clock_valid() local
2411 for (i = 0U; i < ARRAY_SIZE(pm_clk_invalid_list); i++) { in pm_clock_valid()
2412 if (pm_clk_invalid_list[i] == clock_id) { in pm_clock_valid()
2498 uint32_t i; in pm_api_clock_get_topology() local
2521 for (i = 0; i < 3U; i++) { in pm_api_clock_get_topology()
2522 if ((index + i) == num_nodes) { in pm_api_clock_get_topology()
2526 topology[i] = clock_nodes[index + i].type; in pm_api_clock_get_topology()
2527 topology[i] |= ((uint32_t)clock_nodes[index + i].clkflags << in pm_api_clock_get_topology()
2529 typeflags = clock_nodes[index + i].typeflags; in pm_api_clock_get_topology()
2530 topology[i] |= ((uint32_t)(typeflags & CLK_TYPEFLAGS_BITS_MASK) << in pm_api_clock_get_topology()
[all …]
/rk3399_ARM-atf/plat/qti/common/src/
H A Dqti_gic_v3.c125 unsigned int i; in plat_qti_gic_init() local
132 for (i = 0; i < ARRAY_SIZE(qti_interrupt_props); i++) { in plat_qti_gic_init()
133 unsigned int int_id = qti_interrupt_props[i].intr_num; in plat_qti_gic_init()
/rk3399_ARM-atf/plat/marvell/armada/a3k/common/
H A Dcm3_system_reset.c65 int i; in a3700_gic_dist_disable_irqs() local
67 for (i = 32; i < 224; i += 32) { in a3700_gic_dist_disable_irqs()
68 a3700_gicd_write(GICD_ICENABLER + (i >> 3), GENMASK_32(31, 0)); in a3700_gic_dist_disable_irqs()
/rk3399_ARM-atf/plat/mediatek/mt8183/
H A Dplat_mt_gic.c52 unsigned int i; in clear_sec_pol_ctl_en() local
55 for (i = 0; i <= NR_INT_POL_CTL - 1; i++) { in clear_sec_pol_ctl_en()
56 mmio_write_32((SEC_POL_CTL_EN0 + (i * 4)), 0); in clear_sec_pol_ctl_en()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mq/
H A Dimx8mq_psci.c123 unsigned int i; in imx_get_sys_suspend_power_state() local
125 for (i = IMX_PWR_LVL0; i < PLAT_MAX_PWR_LVL; i++) in imx_get_sys_suspend_power_state()
126 req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE; in imx_get_sys_suspend_power_state()
/rk3399_ARM-atf/plat/qemu/common/
H A Dqemu_spm.c64 unsigned int i, j; in qemu_initialize_mp_info() local
67 for (i = 0; i < PLATFORM_CLUSTER_COUNT; i++) { in qemu_initialize_mp_info()
69 tmp->mpidr = (0x80000000 | (i << MPIDR_AFF1_SHIFT)) + j; in qemu_initialize_mp_info()
/rk3399_ARM-atf/drivers/arm/cci/
H A Dcci.c41 size_t i; in validate_cci_map() local
44 for (i = 0U; i <= max_master_id; i++) { in validate_cci_map()
45 slave_if_id = map[i]; in validate_cci_map()
/rk3399_ARM-atf/drivers/gpio/
H A Dgpio_spi.c78 for (int i = 7; i >= 0; i--) { in xfer() local
83 gpio_spi_mosi(!!(out_byte & (1 << i))); in xfer()
89 in_byte |= gpio_spi_miso() << i; in xfer()
/rk3399_ARM-atf/drivers/marvell/secure_dfx_access/
H A Darmada_thermal.c130 int i; in armada_mc_to_reg_hyst() local
137 for (i = ARRAY_SIZE(hyst_levels_mc) - 1; i > 0; i--) in armada_mc_to_reg_hyst()
138 if (hyst_mc >= hyst_levels_mc[i]) in armada_mc_to_reg_hyst()
141 return i; in armada_mc_to_reg_hyst()
/rk3399_ARM-atf/drivers/marvell/mochi/
H A Dcp110_setup.c219 int i = 0; in cp110_stream_id_init() local
221 while (stream_id_reg[i]) { in cp110_stream_id_init()
222 if (i > MAX_STREAM_ID_PER_CP) { in cp110_stream_id_init()
228 if ((stream_id_reg[i] == CP_DMA_0_STREAM_ID_REG) || in cp110_stream_id_init()
229 (stream_id_reg[i] == CP_DMA_1_STREAM_ID_REG)) in cp110_stream_id_init()
230 mmio_write_32(base + stream_id_reg[i], in cp110_stream_id_init()
233 mmio_write_32(base + stream_id_reg[i], stream_id); in cp110_stream_id_init()
238 if (stream_id_reg[i] != SATA_0_STREAM_ID_REG) in cp110_stream_id_init()
241 i++; in cp110_stream_id_init()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mm/
H A Dgpc.c312 int i; in imx_gpc_init() local
315 for (i = 0; i < 4; i++) { in imx_gpc_init()
316 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); in imx_gpc_init()
317 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); in imx_gpc_init()
318 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0); in imx_gpc_init()
319 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); in imx_gpc_init()
320 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); in imx_gpc_init()
/rk3399_ARM-atf/drivers/renesas/rcar_gen4/pwrc/
H A Dpwrc.c235 uint32_t cpu, i, j, reg; in rcar_pwrc_setup() local
243 for (i = 0; i < PLATFORM_CLUSTER_COUNT; i++) { in rcar_pwrc_setup()
249 mmio_setbits_32(apsreg_ap_cluster_aux0(i), in rcar_pwrc_setup()
253 cpu = (i * PLATFORM_MAX_CPUS_PER_CLUSTER) + j; in rcar_pwrc_setup()
285 uint32_t core_pos, cpu, i, j, prr, state; in rcar_pwrc_cpu_on_check() local
290 for (i = 0; i < PLATFORM_CLUSTER_COUNT; i++) { in rcar_pwrc_cpu_on_check()
298 cpu = (i * PLATFORM_MAX_CPUS_PER_CLUSTER) + j; in rcar_pwrc_cpu_on_check()
/rk3399_ARM-atf/plat/imx/imx8qm/
H A Dimx8qm_bl31_setup.c182 int i; in mx8_partition_resources() local
192 for (i = 0; i < ARRAY_SIZE(secure_rsrcs); i++) { in mx8_partition_resources()
193 err = sc_rm_set_resource_movable(ipc_handle, secure_rsrcs[i], in mx8_partition_resources()
194 secure_rsrcs[i], false); in mx8_partition_resources()
197 secure_rsrcs[i], err); in mx8_partition_resources()
223 for (i = 0; i < ARRAY_SIZE(ns_access_allowed); i++) { in mx8_partition_resources()
224 err = sc_rm_set_peripheral_permissions(ipc_handle, ns_access_allowed[i], in mx8_partition_resources()
228 ret %u\n", ns_access_allowed[i], err); in mx8_partition_resources()
/rk3399_ARM-atf/plat/imx/imx8m/ddr/
H A Dddr4_dvfs.c87 for (int i = 1; i <= num_rank; i++) { in dram_cfg_all_mr() local
89 ddr4_mr_write(j, info->mr_table[pstate][j], 0, i, dram_type); in dram_cfg_all_mr()
91 ddr4_mr_write(6, info->mr_table[pstate][7], 0, i, dram_type); in dram_cfg_all_mr()
/rk3399_ARM-atf/plat/intel/soc/common/drivers/sdmmc/
H A Dsdmmc.c55 int i; in sdmmc_send_cmd() local
57 for (i = 0; i < 4; i++) { in sdmmc_send_cmd()
58 *r_data = cmd.resp_data[i]; in sdmmc_send_cmd()
/rk3399_ARM-atf/plat/mediatek/drivers/pmic/mt8196/
H A Dpmic_lowpower_init.c30 uint8_t i, slvid; in pmic_lowpower_init() local
32 for (i = 0; i < ARRAY_SIZE(lowpower_slvid_arr); i++) { in pmic_lowpower_init()
33 slvid = lowpower_slvid_arr[i]; in pmic_lowpower_init()
/rk3399_ARM-atf/plat/st/common/
H A Dstm32mp_crypto_lib.c488 size_t i, j; in derive_key() local
498 for (i = 0U, j = len; j < 32U; in derive_key()
499 i += sizeof(uint32_t), j += sizeof(uint32_t)) { in derive_key()
500 memcpy(key + j, key + i, sizeof(uint32_t)); in derive_key()
517 size_t i; in plat_get_enc_key_info() local
537 for (i = 0U; i < read_len / sizeof(uint32_t); i++) { in plat_get_enc_key_info()
541 if (stm32_get_otp_value_from_idx(otp_idx + i, &otp_val) != 0) { in plat_get_enc_key_info()
548 memcpy(key + i * sizeof(uint32_t), &tmp, sizeof(tmp)); in plat_get_enc_key_info()
583 unsigned int i; in stm32_decrypt_aes_gcm() local
609 for (i = 0U; i < tag_len; i++) { in stm32_decrypt_aes_gcm()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/version/notifier/v4/
H A Dmt_spm_sspm_notifier.c62 int i = 0; in __mt_spm_get_available_index() local
64 for (i = 0 ; i < SSPM_MBOX_SPM_SIZE ; i++) { in __mt_spm_get_available_index()
/rk3399_ARM-atf/drivers/renesas/common/scif/
H A Dscif.c56 int i; in console_renesas_init() local
110 for (i = 0; i < 100; i++) in console_renesas_init()
/rk3399_ARM-atf/plat/nxp/soc-ls1088a/
H A Dsoc.c66 unsigned int i; in plat_get_power_domain_tree_desc() local
78 for (i = 0; i < _power_domain_tree_desc[1]; i++) { in plat_get_power_domain_tree_desc()
79 _power_domain_tree_desc[i + 2] = cores_per_cluster; in plat_get_power_domain_tree_desc()
203 int i = 0; in soc_mem_access() local
209 if (info_dram_regions->region[i].size == 0) { in soc_mem_access()
/rk3399_ARM-atf/drivers/marvell/
H A Dio_win.c119 for (int i = 0; i < size; i++) { in iow_temp_win_insert() local
120 win_id = MVEBU_IO_WIN_MAX_WINS - i - 1; in iow_temp_win_insert()
136 for (int i = 0; i < size; i++) { in iow_temp_win_remove() local
140 win_id = MVEBU_IO_WIN_MAX_WINS - i - 1; in iow_temp_win_remove()
/rk3399_ARM-atf/plat/allwinner/sun50i_a64/
H A Dsunxi_power.c42 int i; in sunxi_turn_off_soc() local
75 for (i = 0; i < 6; i++) in sunxi_turn_off_soc()
76 mmio_clrbits_32(SUNXI_CCU_BASE + i * 8, BIT(31)); in sunxi_turn_off_soc()

1...<<11121314151617181920>>...25