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/rk3399_rockchip-uboot/drivers/pinctrl/rockchip/
H A Dpinctrl-rockchip-core.c46 int i; in rockchip_get_recalced_mux() local
48 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux()
49 data = &ctrl->iomux_recalced[i]; in rockchip_get_recalced_mux()
55 if (i >= ctrl->niomux_recalced) in rockchip_get_recalced_mux()
70 int i; in rockchip_get_mux_route() local
72 for (i = 0; i < ctrl->niomux_routes; i++) { in rockchip_get_mux_route()
73 data = &ctrl->iomux_routes[i]; in rockchip_get_mux_route()
79 if (i >= ctrl->niomux_routes) in rockchip_get_mux_route()
261 int i, ret; in rockchip_translate_drive_value() local
264 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[type]); i++) { in rockchip_translate_drive_value()
[all …]
/rk3399_rockchip-uboot/drivers/net/
H A Dmcffec.c402 int i; in fec_init() local
478 for (i = 0; i < PKTBUFSRX; i++) { in fec_init()
479 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; in fec_init()
480 info->rxbd[i].cbd_datlen = 0; /* Reset */ in fec_init()
481 info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; in fec_init()
490 for (i = 0; i < TX_BUF_CNT; i++) { in fec_init()
491 info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; in fec_init()
492 info->txbd[i].cbd_datlen = 0; /* Reset */ in fec_init()
493 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); in fec_init()
514 int i; in fec_reset() local
[all …]
H A Dftgmac100.c50 int i; in ftgmac100_mdiobus_read() local
63 for (i = 0; i < 10; i++) { in ftgmac100_mdiobus_read()
86 int i; in ftgmac100_mdiobus_write() local
102 for (i = 0; i < 10; i++) { in ftgmac100_mdiobus_write()
139 int i; in ftgmac100_phy_reset() local
151 for (i = 0; i < 100000 / 100; i++) { in ftgmac100_phy_reset()
177 int i; in ftgmac100_phy_init() local
207 for (i = 0; i < 100000 / 100; i++) { in ftgmac100_phy_init()
374 int i; in ftgmac100_init() local
411 for (i = 0; i < PKTBUFSTX; i++) { in ftgmac100_init()
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H A Dfsl_mcdmafec.c355 int i; in fec_init() local
400 for (i = 0; i < PKTBUFSRX; i++) { in fec_init()
401 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; in fec_init()
402 info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN; in fec_init()
403 info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; in fec_init()
409 for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) { in fec_init()
410 info->txbd[i].cbd_sc = 0; in fec_init()
411 info->txbd[i].cbd_datlen = 0; in fec_init()
412 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); in fec_init()
503 int i; in mcdmafec_initialize() local
[all …]
/rk3399_rockchip-uboot/drivers/dma/
H A DMCD_dmaApi.c132 int i; in MCD_initDma() local
149 int i; in MCD_initDma() local
191 for (i = 0; i < (fixedSize / 4); i++) in MCD_initDma()
192 fixedPtr[i] = 0; in MCD_initDma()
196 for (i = 0; i < NCHANNELS; i++) { in MCD_initDma()
198 entryPtr[i].varTab = (u32) varTabsOffset; in MCD_initDma()
199 entryPtr[i].FDTandFlags = in MCD_initDma()
201 entryPtr[i].contextSaveSpace = (u32) contextSavesOffset; in MCD_initDma()
211 for (i = 0; i < FUNCDESC_TAB_NUM; i++) { in MCD_initDma()
212 MCD_memcpy((void *)(entryPtr[i]. in MCD_initDma()
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/rk3399_rockchip-uboot/lib/
H A Dslre.c99 int i; in print_character_set() local
101 for (i = 0; i < len; i++) { in print_character_set()
102 if (i > 0) in print_character_set()
104 if (p[i] == 0) { in print_character_set()
105 i++; in print_character_set()
106 if (p[i] == 0) in print_character_set()
107 (void) fprintf(fp, "\\x%02x", p[i]); in print_character_set()
109 (void) fprintf(fp, "%s", opcodes[p[i]].name); in print_character_set()
110 } else if (isprint(p[i])) { in print_character_set()
111 (void) fputc(p[i], fp); in print_character_set()
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/rk3399_rockchip-uboot/drivers/ddr/fsl/
H A Dctrl_regs.c148 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, in set_csn_config() argument
169 switch (i) { in set_csn_config()
211 ap_n_en = popts->cs_local_opts[i].auto_precharge; in set_csn_config()
212 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; in set_csn_config()
213 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; in set_csn_config()
225 ddr->cs[i].config = (0 in set_csn_config()
244 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); in set_csn_config()
249 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) in set_csn_config_2() argument
253 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); in set_csn_config_2()
254 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); in set_csn_config_2()
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/rk3399_rockchip-uboot/test/dm/
H A Dpmic.c48 int reg_count, i; in dm_test_power_pmic_io() local
60 for (i = 0; i < reg_count; i++) { in dm_test_power_pmic_io()
61 out_buffer = i; in dm_test_power_pmic_io()
62 ut_assertok(pmic_write(dev, i, &out_buffer, 1)); in dm_test_power_pmic_io()
63 ut_assertok(pmic_read(dev, i, &in_buffer, 1)); in dm_test_power_pmic_io()
/rk3399_rockchip-uboot/board/freescale/bsc9132qds/
H A Dddr.c86 int i; in fixed_sdram() local
98 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { in fixed_sdram()
99 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && in fixed_sdram()
100 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { in fixed_sdram()
101 memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, in fixed_sdram()
107 if (fixed_ddr_parm_0[i].max_freq == 0) in fixed_sdram()
174 int i; in fsl_ddr_board_options() local
187 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { in fsl_ddr_board_options()
188 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; in fsl_ddr_board_options()
189 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; in fsl_ddr_board_options()
/rk3399_rockchip-uboot/drivers/irq/
H A Dirq-gic.c232 int irq_nr, i, irq; in gic_irq_suspend() local
255 for (i = 0, irq = 0; irq < irq_nr; irq += 16) in gic_irq_suspend()
256 gicd_save.icfgr[i++] = in gic_irq_suspend()
259 for (i = 0, irq = 0; irq < irq_nr; irq += 4) in gic_irq_suspend()
260 gicd_save.itargetsr[i++] = in gic_irq_suspend()
263 for (i = 0, irq = 0; irq < irq_nr; irq += 4) in gic_irq_suspend()
264 gicd_save.ipriorityr[i++] = in gic_irq_suspend()
267 for (i = 0, irq = 0; irq < irq_nr; irq += 32) in gic_irq_suspend()
268 gicd_save.igroupr[i++] = in gic_irq_suspend()
271 for (i = 0, irq = 0; irq < irq_nr; irq += 32) in gic_irq_suspend()
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/rk3399_rockchip-uboot/cmd/
H A Ddisplay.c16 int i; in do_display() local
24 for (i = 1; i < argc; i++) { in do_display()
25 char *p = argv[i]; in do_display()
27 if (i > 1) { /* Insert a space between strings */ in do_display()
/rk3399_rockchip-uboot/drivers/rkflash/
H A Dnandc.c98 u32 i; in nandc_wait_flash_ready() local
101 for (i = 0; i < 100000; i++) { in nandc_wait_flash_ready()
108 if (i >= 100000) in nandc_wait_flash_ready()
193 u32 i; in nandc_xfer_start() local
211 for (i = 0; i < n_sec / 2; i++) { in nandc_xfer_start()
213 master.spare_buf[i] = in nandc_xfer_start()
218 master.spare_buf[i] = 0xffffffff; in nandc_xfer_start()
274 for (i = 0; i < n_sec / 2; i++) { in nandc_xfer_start()
276 master.spare_buf[i * spare_sz / 4] = in nandc_xfer_start()
281 master.spare_buf[i * spare_sz / 4] = in nandc_xfer_start()
[all …]
/rk3399_rockchip-uboot/drivers/mtd/nand/raw/
H A Dkmeter1_nand.c81 int i; in kpn_nand_write_buf() local
83 for (i = 0; i < len; i++) { in kpn_nand_write_buf()
84 write_data(buf[i]); in kpn_nand_write_buf()
91 int i; in kpn_nand_read_buf() local
93 for (i = 0; i < len; i++) in kpn_nand_read_buf()
94 buf[i] = read_data(); in kpn_nand_read_buf()
H A Dsunxi_nand.c1012 int ret, i, cur_off = 0; in sunxi_nfc_hw_ecc_read_page() local
1017 for (i = 0; i < ecc->steps; i++) { in sunxi_nfc_hw_ecc_read_page()
1018 int data_off = i * ecc->size; in sunxi_nfc_hw_ecc_read_page()
1019 int oob_off = i * (ecc->bytes + 4); in sunxi_nfc_hw_ecc_read_page()
1026 !i, page); in sunxi_nfc_hw_ecc_read_page()
1048 int ret, i, cur_off = 0; in sunxi_nfc_hw_ecc_read_subpage() local
1054 for (i = data_offs / ecc->size; in sunxi_nfc_hw_ecc_read_subpage()
1055 i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) { in sunxi_nfc_hw_ecc_read_subpage()
1056 int data_off = i * ecc->size; in sunxi_nfc_hw_ecc_read_subpage()
1057 int oob_off = i * (ecc->bytes + 4); in sunxi_nfc_hw_ecc_read_subpage()
[all …]
/rk3399_rockchip-uboot/drivers/clk/uniphier/
H A Dclk-uniphier-core.c69 int i; in uniphier_clk_get_rate() local
80 for (i = 0; i < mux->nr_muxs; i++) in uniphier_clk_get_rate()
81 if ((mux->masks[i] & val) == mux->vals[i]) in uniphier_clk_get_rate()
82 return mux->rates[i]; in uniphier_clk_get_rate()
92 int i, best_rate_id = -1; in uniphier_clk_set_rate() local
103 for (i = 0; i < mux->nr_muxs; i++) { in uniphier_clk_set_rate()
104 if (mux->rates[i] > best_rate && mux->rates[i] <= rate) { in uniphier_clk_set_rate()
105 best_rate = mux->rates[i]; in uniphier_clk_set_rate()
106 best_rate_id = i; in uniphier_clk_set_rate()
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/
H A Dsoc-info.h32 int i; \
35 for (i = 0; i < ARRAY_SIZE(__table); i++) { \
36 if (__table[i].soc_id == soc_id) \
37 return &__table[i]; \
/rk3399_rockchip-uboot/drivers/pci/
H A Dpci_mvebu.c289 int i; in mvebu_pcie_setup_wins() local
292 for (i = 1; i < 3; i++) { in mvebu_pcie_setup_wins()
293 writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i)); in mvebu_pcie_setup_wins()
294 writel(0, pcie->base + PCIE_BAR_LO_OFF(i)); in mvebu_pcie_setup_wins()
295 writel(0, pcie->base + PCIE_BAR_HI_OFF(i)); in mvebu_pcie_setup_wins()
298 for (i = 0; i < 5; i++) { in mvebu_pcie_setup_wins()
299 writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i)); in mvebu_pcie_setup_wins()
300 writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i)); in mvebu_pcie_setup_wins()
301 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i)); in mvebu_pcie_setup_wins()
310 for (i = 0; i < dram->num_cs; i++) { in mvebu_pcie_setup_wins()
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/rk3399_rockchip-uboot/drivers/video/bridge/
H A Danx6345.c177 int i, ret; in anx6345_aux_transfer() local
190 for (i = 0; i < len; i++) in anx6345_aux_transfer()
191 anx6345_write_r0(dev, ANX9804_BUF_DATA_0 + i, buf[i]); in anx6345_aux_transfer()
204 for (i = 0; i < len; i++) in anx6345_aux_transfer()
205 anx6345_read_r0(dev, ANX9804_BUF_DATA_0 + i, &buf[i]); in anx6345_aux_transfer()
214 int i, ret; in anx6345_read_aux_i2c() local
218 for (i = 0; i < count; i += 16) { in anx6345_read_aux_i2c()
219 cur_cnt = (count - i) > 16 ? 16 : count - i; in anx6345_read_aux_i2c()
220 cur_offset = offset + i; in anx6345_read_aux_i2c()
229 chip_addr, buf + i, cur_cnt); in anx6345_read_aux_i2c()
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/rk3399_rockchip-uboot/fs/yaffs2/
H A Dyaffs_ecc.c74 unsigned int i; in yaffs_ecc_calc() local
81 for (i = 0; i < 256; i++) { in yaffs_ecc_calc()
86 line_parity ^= i; in yaffs_ecc_calc()
87 line_parity_prime ^= ~i; in yaffs_ecc_calc()
208 unsigned int i; in yaffs_ecc_calc_other() local
214 for (i = 0; i < n_bytes; i++) { in yaffs_ecc_calc_other()
220 line_parity ^= i; in yaffs_ecc_calc_other()
221 line_parity_prime ^= ~i; in yaffs_ecc_calc_other()
/rk3399_rockchip-uboot/drivers/ata/
H A Dmvsata_ide.c109 int i; in mvsata_ide_conf_mbus_windows() local
114 for (i = 0; i < 4; i++) { in mvsata_ide_conf_mbus_windows()
115 writel(0, MVSATA_WIN_CONTROL(i)); in mvsata_ide_conf_mbus_windows()
116 writel(0, MVSATA_WIN_BASE(i)); in mvsata_ide_conf_mbus_windows()
119 for (i = 0; i < dram->num_cs; i++) { in mvsata_ide_conf_mbus_windows()
120 const struct mbus_dram_window *cs = dram->cs + i; in mvsata_ide_conf_mbus_windows()
123 MVSATA_WIN_CONTROL(i)); in mvsata_ide_conf_mbus_windows()
124 writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i)); in mvsata_ide_conf_mbus_windows()
/rk3399_rockchip-uboot/common/
H A Dedid.c1723 int i; in edid_check_checksum() local
1725 for (i = 0; i < 128; i++) in edid_check_checksum()
1726 checksum += edid_block[i]; in edid_check_checksum()
1735 int i; in edid_get_ranges() local
1742 for (i = 0; i < ARRAY_SIZE(edid->monitor_details.descriptor); i++) { in edid_get_ranges()
1743 monitor = &edid->monitor_details.descriptor[i]; in edid_get_ranges()
1907 u8 end, i = 0; in cea_is_hdmi_vsdb_present() local
1917 while (i < end) { in cea_is_hdmi_vsdb_present()
1919 if ((EDID_CEA861_DB_TYPE(*info, i) == EDID_CEA861_DB_VENDOR) && in cea_is_hdmi_vsdb_present()
1920 (EDID_CEA861_DB_LEN(*info, i) >= 5)) { in cea_is_hdmi_vsdb_present()
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H A Dbootstage.c54 int i; in bootstage_relocate() local
61 for (i = 0; i < data->rec_count; i++) in bootstage_relocate()
62 data->record[i].name = strdup(data->record[i].name); in bootstage_relocate()
256 int i; in add_bootstages_devicetree() local
273 for (recnum = data->rec_count - 1, i = 0; recnum >= 0; recnum--, i++) { in add_bootstages_devicetree()
280 node = fdt_add_subnode(blob, bootstage, simple_itoa(i)); in add_bootstages_devicetree()
313 int i; in bootstage_report() local
324 for (i = 1, rec++; i < data->rec_count; i++, rec++) { in bootstage_report()
334 for (i = 0, rec = data->record; i < data->rec_count; i++, rec++) { in bootstage_report()
370 int i; in bootstage_stash() local
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/rk3399_rockchip-uboot/board/samsung/trats2/
H A Dtrats2.c37 int i; in check_hw_revision() local
45 for (i = 0; i < 2; i++) { in check_hw_revision()
46 int pin = i + EXYNOS4X12_GPIO_M10; in check_hw_revision()
48 sprintf(str, "model_rev%d", i); in check_hw_revision()
54 for (i = 0; i < 4; i++) { in check_hw_revision()
55 int pin = i + EXYNOS4X12_GPIO_M12; in check_hw_revision()
57 sprintf(str, "hw_rev%d", i); in check_hw_revision()
64 for (i = 0; i < 2; i++) in check_hw_revision()
65 modelrev |= (gpio_get_value(EXYNOS4X12_GPIO_M10 + i) << i); in check_hw_revision()
/rk3399_rockchip-uboot/fs/ext4/
H A Dext4_write.c69 short i; in ext4fs_update() local
79 for (i = 0; i < fs->no_blkgrp; i++) { in ext4fs_update()
80 bgd = ext4fs_get_group_descriptor(fs, i); in ext4fs_update()
81 bgd->bg_checksum = cpu_to_le16(ext4fs_checksum_update(i)); in ext4fs_update()
84 fs->blk_bmaps[i], fs->blksz); in ext4fs_update()
88 for (i = 0; i < fs->no_blkgrp; i++) { in ext4fs_update()
89 bgd = ext4fs_get_group_descriptor(fs, i); in ext4fs_update()
92 fs->inode_bmaps[i], fs->blksz); in ext4fs_update()
186 int i; in delete_double_indirect_block() local
213 for (i = 0; i < fs->blksz / sizeof(int); i++) { in delete_double_indirect_block()
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/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap5/
H A Dhwinit.c48 int i; in do_set_mux32() local
51 for (i = 0; i < size; i++, pad++) in do_set_mux32()
202 u32 srcomp_value, mul_factor, div_factor, clk_val, i; in srcomp_enable() local
212 for (i = 0; i < 4; i++) { in srcomp_enable()
213 srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4); in srcomp_enable()
218 writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4); in srcomp_enable()
226 for (i = 0; i < 4; i++) { in srcomp_enable()
228 readl((*ctrl)->control_srcomp_north_side + i*4); in srcomp_enable()
231 (*ctrl)->control_srcomp_north_side + i*4); in srcomp_enable()
233 while (((readl((*ctrl)->control_srcomp_north_side + i*4) in srcomp_enable()
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