1 /*
2 * Copyright (c) 2025, Mediatek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <errno.h>
8
9 #include <common/debug.h>
10 #include <drivers/pmic/pmic_set_lowpower.h>
11 #include <drivers/pmic/pmic_swap_api.h>
12 #include <drivers/spmi/spmi_common.h>
13 #include <lib/mtk_init/mtk_init.h>
14
15 #define MASTER_ID SPMI_MASTER_1
16
17 struct spmi_device *lowpower_sdev[SPMI_MAX_SLAVE_ID];
18
19 static const uint8_t lowpower_slvid_arr[] = {
20 MT6363_SLAVE,
21 MT6373_SLAVE,
22 MT6316_S6_SLAVE,
23 MT6316_S7_SLAVE,
24 MT6316_S8_SLAVE,
25 MT6316_S15_SLAVE,
26 };
27
pmic_lowpower_init(void)28 static int pmic_lowpower_init(void)
29 {
30 uint8_t i, slvid;
31
32 for (i = 0; i < ARRAY_SIZE(lowpower_slvid_arr); i++) {
33 slvid = lowpower_slvid_arr[i];
34 lowpower_sdev[slvid] = get_spmi_device(MASTER_ID, slvid);
35 if (!lowpower_sdev[slvid])
36 return -ENODEV;
37 }
38
39 /* MT6363 Deep idle, SODI3 */
40 /* VREQ config by SCP owner in LK2 */
41 PMIC_BUCK_SET_LP(MT6363, VBUCK4, HW2, true, OP_MODE_LP, HW_LP);
42 PMIC_BUCK_SET_LP(MT6363, VBUCK4, RC9, true, OP_MODE_MU, HW_ON);
43 PMIC_BUCK_SET_LP(MT6363, VS2, HW2, true, OP_MODE_LP, HW_LP);
44 PMIC_BUCK_SET_LP(MT6363, VS2, RC9, true, OP_MODE_MU, HW_ON);
45 PMIC_BUCK_SET_LP(MT6363, VS3, HW2, true, OP_MODE_LP, HW_LP);
46 PMIC_LDO_SET_LP(MT6363, VSRAM_CPUB, HW2, true, OP_MODE_LP, HW_LP);
47 PMIC_LDO_SET_LP(MT6363, VSRAM_CPUB, RC9, true, OP_MODE_MU, HW_ON);
48 PMIC_LDO_SET_LP(MT6363, VSRAM_CPUL, HW2, true, OP_MODE_LP, HW_LP);
49 PMIC_LDO_SET_LP(MT6363, VSRAM_CPUL, RC9, true, OP_MODE_MU, HW_ON);
50 PMIC_LDO_SET_LP(MT6363, VSRAM_APU, RC2, true, OP_MODE_MU, HW_OFF);
51 PMIC_LDO_SET_LP(MT6363, VSRAM_MODEM, HW2, true, OP_MODE_LP, HW_LP);
52 PMIC_LDO_SET_LP(MT6363, VSRAM_MODEM, RC9, true, OP_MODE_MU, HW_ON);
53 PMIC_LDO_SET_LP(MT6363, VA12_1, HW2, true, OP_MODE_LP, HW_LP);
54 PMIC_LDO_SET_LP(MT6363, VA12_1, RC9, true, OP_MODE_MU, HW_ON);
55 PMIC_LDO_SET_LP(MT6363, VA12_2, HW2, true, OP_MODE_LP, HW_LP);
56 PMIC_LDO_SET_LP(MT6363, VA12_2, RC9, true, OP_MODE_MU, HW_ON);
57 PMIC_LDO_SET_LP(MT6363, VUFS18, HW2, true, OP_MODE_LP, HW_LP);
58 PMIC_LDO_SET_LP(MT6363, VUFS18, RC9, true, OP_MODE_MU, HW_ON);
59 PMIC_LDO_SET_LP(MT6363, VUFS12, HW2, true, OP_MODE_LP, HW_LP);
60
61 /* MT6373 Deep idle, SODI3 */
62 PMIC_BUCK_SET_LP(MT6373, VBUCK4, HW2, true, OP_MODE_LP, HW_OFF);
63 PMIC_BUCK_SET_LP(MT6373, VBUCK5, HW2, true, OP_MODE_LP, HW_OFF);
64 PMIC_BUCK_SET_LP(MT6373, VBUCK6, HW2, true, OP_MODE_LP, HW_LP);
65 PMIC_LDO_SET_LP(MT6373, VUSB, HW2, true, OP_MODE_LP, HW_LP);
66
67 /* MT6316 Deep idle, SODI3 */
68 PMIC_SLVID_BUCK_SET_LP(MT6316, S8, VBUCK1, HW2, true, OP_MODE_LP, HW_LP);
69 PMIC_SLVID_BUCK_SET_LP(MT6316, S6, VBUCK3, HW2, true, OP_MODE_LP, HW_ONLV);
70 return 0;
71 }
72
73 MTK_PLAT_SETUP_0_INIT(pmic_lowpower_init);
74