| #
c99e3b74 |
| 14-Oct-2025 |
Yann Gautier <yann.gautier@st.com> |
Merge "fix(nxp): tbbr: adds snvs_init" into integration
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| #
ce9b87e7 |
| 13-May-2025 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
fix(nxp): tbbr: adds snvs_init
Fix to initialize the SNVS driver as part of soc early init, that sets
the snvs base address to read or write to the memory mapped registers of
SNVS IP.
Change-Id: I6
fix(nxp): tbbr: adds snvs_init
Fix to initialize the SNVS driver as part of soc early init, that sets
the snvs base address to read or write to the memory mapped registers of
SNVS IP.
Change-Id: I6ebd1d17302647487ec786f5e20f51450ce29473
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
show more ...
|
| #
79664cfc |
| 15-Dec-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I2b23e7c8,I779587af,Ic46de7a4,If753e987,I00171b05, ... into integration
* changes:
fix(layerscape): unlock write access SMMU_CBn_ACTLR
fix(nxp-ddr): add checking return value
fea
Merge changes I2b23e7c8,I779587af,Ic46de7a4,If753e987,I00171b05, ... into integration
* changes:
fix(layerscape): unlock write access SMMU_CBn_ACTLR
fix(nxp-ddr): add checking return value
feat(lx2): enable OCRAM ECC
fix(nxp-tools): fix coverity issue
fix(nxp-ddr): fix coverity issue
fix(nxp-ddr): fix underrun coverity issue
fix(nxp-drivers): fix sd secure boot failure
feat(lx2): support more variants
fix(lx2): init global data before using it
fix(ls1046a): 4 keys secureboot failure resolved
fix(nxp-crypto): fix secure boot assert inclusion
fix(nxp-crypto): fix coverity issue
fix(nxp-drivers): fix fspi coverity issue
fix(nxp-drivers): fix tzc380 memory regions config
fix(layerscape): fix nv_storage assert checking
fix(nxp-ddr): apply Max CDD values for warm boot
fix(nxp-ddr): use CDDWW for write to read delay
fix(layerscape): fix errata a008850
show more ...
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| #
0ca1d8fb |
| 01-Nov-2022 |
Howard Lu <howard.lu@nxp.com> |
fix(layerscape): unlock write access SMMU_CBn_ACTLR
This patch is to fix Errata #841119 and #826419 failed apply in linux
because of SMMU_CBn_ACTLR register can't be modified in non-secure
states.
fix(layerscape): unlock write access SMMU_CBn_ACTLR
This patch is to fix Errata #841119 and #826419 failed apply in linux
because of SMMU_CBn_ACTLR register can't be modified in non-secure
states.
Signed-off-by: Howard Lu <howard.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I2b23e7c8baa809f385917eb45b10ec6b26a9ada8
show more ...
|
| #
2ea18c7d |
| 28-Mar-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topics "ls1088a", "ls1088a-prepare" into integration
* changes:
docs(layerscape): add ls1088a soc and board support
feat(ls1088aqds): add ls1088aqds board support
feat(ls108
Merge changes from topics "ls1088a", "ls1088a-prepare" into integration
* changes:
docs(layerscape): add ls1088a soc and board support
feat(ls1088aqds): add ls1088aqds board support
feat(ls1088ardb): add ls1088ardb board support
feat(ls1088a): add new SoC platform ls1088a
build(changelog): add new scopes for ls1088a
feat(bl2): add support to separate no-loadable sections
refactor(layerscape): refine comparison of inerconnection
feat(layerscape): add soc helper macro definition for chassis 3
feat(nxp-gic): add some macros definition for gicv3
feat(layerscape): add CHASSIS 3 support for tbbr
feat(layerscape): define more chassis 3 hardware address
feat(nxp-crypto): add chassis 3 support
feat(nxp-dcfg): add Chassis 3 support
feat(lx2): enable DDR erratas for lx2 platforms
feat(layerscape): print DDR errata information
feat(nxp-ddr): add workaround for errata A050958
feat(layerscape): add new soc errata a010539 support
feat(layerscape): add new soc errata a009660 support
feat(nxp-ddr): add rawcard 1F support
fix(layerscape): fix build issue of mmap_add_ddr_region_dynamically
fix(nxp-tools): fix create_pbl print log
build(changelog): add new scopes for NXP driver
show more ...
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| #
9df5ba05 |
| 18-Feb-2022 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(ls1088a): add new SoC platform ls1088a
LS1088A is a cost-effective, powerefficient, and highly integrated
SoC device featuring eight extremely power-efficient 64-bit ARM
Cortex-A53 cores with E
feat(ls1088a): add new SoC platform ls1088a
LS1088A is a cost-effective, powerefficient, and highly integrated
SoC device featuring eight extremely power-efficient 64-bit ARM
Cortex-A53 cores with ECC-protected L1 and L2 cache memories for
high reliability, running up to 1.6 GHz.
This patch is to add ls1088a SoC support in TF-A.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Id9ebcdad1beab07ea81a41955edd4f471d6cf090
show more ...
|