1 /*
2 * Copyright (C) 2018-2020 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8 /* CP110 Marvell SoC driver */
9
10 #include <common/debug.h>
11 #include <drivers/delay_timer.h>
12 #include <drivers/marvell/amb_adec.h>
13 #include <drivers/marvell/iob.h>
14 #include <drivers/marvell/mochi/cp110_setup.h>
15
16 #include <efuse_def.h>
17 #include <plat_marvell.h>
18
19 /*
20 * AXI Configuration.
21 */
22
23 /* Used for Units of CP-110 (e.g. USB device, USB Host, and etc) */
24 #define MVEBU_AXI_ATTR_OFFSET (0x441300)
25 #define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_OFFSET + \
26 0x4 * index)
27
28 /* AXI Protection bits */
29 #define MVEBU_AXI_PROT_OFFSET (0x441200)
30
31 /* AXI Protection regs */
32 #define MVEBU_AXI_PROT_REG(index) ((index <= 4) ? \
33 (MVEBU_AXI_PROT_OFFSET + \
34 0x4 * index) : \
35 (MVEBU_AXI_PROT_OFFSET + 0x18))
36 #define MVEBU_AXI_PROT_REGS_NUM (6)
37
38 #define MVEBU_SOC_CFGS_OFFSET (0x441900)
39 #define MVEBU_SOC_CFG_REG(index) (MVEBU_SOC_CFGS_OFFSET + \
40 0x4 * index)
41 #define MVEBU_SOC_CFG_REG_NUM (0)
42 #define MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK (0xE)
43
44 /* SATA3 MBUS to AXI regs */
45 #define MVEBU_BRIDGE_WIN_DIS_REG (MVEBU_SOC_CFGS_OFFSET + 0x10)
46 #define MVEBU_BRIDGE_WIN_DIS_OFF (0x0)
47
48 /* SATA3 MBUS to AXI regs */
49 #define MVEBU_SATA_M2A_AXI_PORT_CTRL_REG (0x54ff04)
50
51 /* AXI to MBUS bridge registers */
52 #define MVEBU_AMB_IP_OFFSET (0x13ff00)
53 #define MVEBU_AMB_IP_BRIDGE_WIN_REG(win) (MVEBU_AMB_IP_OFFSET + \
54 (win * 0x8))
55 #define MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET 0
56 #define MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK \
57 (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET)
58 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET 16
59 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK \
60 (0xffffu << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET)
61
62 #define MVEBU_SAMPLE_AT_RESET_REG (0x440600)
63 #define SAR_PCIE1_CLK_CFG_OFFSET 31
64 #define SAR_PCIE1_CLK_CFG_MASK (0x1u << SAR_PCIE1_CLK_CFG_OFFSET)
65 #define SAR_PCIE0_CLK_CFG_OFFSET 30
66 #define SAR_PCIE0_CLK_CFG_MASK (0x1 << SAR_PCIE0_CLK_CFG_OFFSET)
67 #define SAR_I2C_INIT_EN_OFFSET 24
68 #define SAR_I2C_INIT_EN_MASK (1 << SAR_I2C_INIT_EN_OFFSET)
69
70 /*******************************************************************************
71 * PCIE clock buffer control
72 ******************************************************************************/
73 #define MVEBU_PCIE_REF_CLK_BUF_CTRL (0x4404F0)
74 #define PCIE1_REFCLK_BUFF_SOURCE 0x800
75 #define PCIE0_REFCLK_BUFF_SOURCE 0x400
76
77 /*******************************************************************************
78 * MSS Device Push Set Register
79 ******************************************************************************/
80 #define MVEBU_CP_MSS_DPSHSR_REG (0x280040)
81 #define MSS_DPSHSR_REG_PCIE_CLK_SEL 0x8
82
83 /*******************************************************************************
84 * RTC Configuration
85 ******************************************************************************/
86 #define MVEBU_RTC_BASE (0x284000)
87 #define MVEBU_RTC_STATUS_REG (MVEBU_RTC_BASE + 0x0)
88 #define MVEBU_RTC_STATUS_ALARM1_MASK 0x1
89 #define MVEBU_RTC_STATUS_ALARM2_MASK 0x2
90 #define MVEBU_RTC_IRQ_1_CONFIG_REG (MVEBU_RTC_BASE + 0x4)
91 #define MVEBU_RTC_IRQ_2_CONFIG_REG (MVEBU_RTC_BASE + 0x8)
92 #define MVEBU_RTC_TIME_REG (MVEBU_RTC_BASE + 0xC)
93 #define MVEBU_RTC_ALARM_1_REG (MVEBU_RTC_BASE + 0x10)
94 #define MVEBU_RTC_ALARM_2_REG (MVEBU_RTC_BASE + 0x14)
95 #define MVEBU_RTC_CCR_REG (MVEBU_RTC_BASE + 0x18)
96 #define MVEBU_RTC_NOMINAL_TIMING 0x2000
97 #define MVEBU_RTC_NOMINAL_TIMING_MASK 0x7FFF
98 #define MVEBU_RTC_TEST_CONFIG_REG (MVEBU_RTC_BASE + 0x1C)
99 #define MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG (MVEBU_RTC_BASE + 0x80)
100 #define MVEBU_RTC_WRCLK_PERIOD_MASK 0xFFFF
101 #define MVEBU_RTC_WRCLK_PERIOD_DEFAULT 0x3FF
102 #define MVEBU_RTC_WRCLK_SETUP_OFFS 16
103 #define MVEBU_RTC_WRCLK_SETUP_MASK 0xFFFF0000
104 #define MVEBU_RTC_WRCLK_SETUP_DEFAULT 0x29
105 #define MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG (MVEBU_RTC_BASE + 0x84)
106 #define MVEBU_RTC_READ_OUTPUT_DELAY_MASK 0xFFFF
107 #define MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT 0x1F
108
109 enum axi_attr {
110 AXI_ADUNIT_ATTR = 0,
111 AXI_COMUNIT_ATTR,
112 AXI_EIP197_ATTR,
113 AXI_USB3D_ATTR,
114 AXI_USB3H0_ATTR,
115 AXI_USB3H1_ATTR,
116 AXI_SATA0_ATTR,
117 AXI_SATA1_ATTR,
118 AXI_DAP_ATTR,
119 AXI_DFX_ATTR,
120 AXI_DBG_TRC_ATTR = 12,
121 AXI_SDIO_ATTR,
122 AXI_MSS_ATTR,
123 AXI_MAX_ATTR,
124 };
125
126 /* Most stream IDS are configured centrally in the CP-110 RFU
127 * but some are configured inside the unit registers
128 */
129 #define RFU_STREAM_ID_BASE (0x450000)
130 #define USB3H_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0xC)
131 #define USB3H_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x10)
132 #define SATA_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x14)
133 #define SATA_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x18)
134 #define SDIO_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x28)
135
136 #define CP_DMA_0_STREAM_ID_REG (0x6B0010)
137 #define CP_DMA_1_STREAM_ID_REG (0x6D0010)
138
139 /* We allocate IDs 128-255 for PCIe */
140 #define MAX_STREAM_ID (0x80)
141
142 static uintptr_t stream_id_reg[] = {
143 USB3H_0_STREAM_ID_REG,
144 USB3H_1_STREAM_ID_REG,
145 CP_DMA_0_STREAM_ID_REG,
146 CP_DMA_1_STREAM_ID_REG,
147 SATA_0_STREAM_ID_REG,
148 SATA_1_STREAM_ID_REG,
149 SDIO_STREAM_ID_REG,
150 0
151 };
152
cp110_errata_wa_init(uintptr_t base)153 static void cp110_errata_wa_init(uintptr_t base)
154 {
155 uint32_t data;
156
157 /* ERRATA GL-4076863:
158 * Reset value for global_secure_enable inputs must be changed
159 * from '1' to '0'.
160 * When asserted, only "secured" transactions can enter IHB
161 * configuration space.
162 * However, blocking AXI transactions is performed by IOB.
163 * Performing it also at IHB/HB complicates programming model.
164 *
165 * Enable non-secure access in SOC configuration register
166 */
167 data = mmio_read_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM));
168 data &= ~MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK;
169 mmio_write_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM), data);
170 }
171
cp110_pcie_clk_cfg(uintptr_t base)172 static void cp110_pcie_clk_cfg(uintptr_t base)
173 {
174 uint32_t pcie0_clk, pcie1_clk, reg;
175
176 /*
177 * Determine the pcie0/1 clock direction (input/output) from the
178 * sample at reset.
179 */
180 reg = mmio_read_32(base + MVEBU_SAMPLE_AT_RESET_REG);
181 pcie0_clk = (reg & SAR_PCIE0_CLK_CFG_MASK) >> SAR_PCIE0_CLK_CFG_OFFSET;
182 pcie1_clk = (reg & SAR_PCIE1_CLK_CFG_MASK) >> SAR_PCIE1_CLK_CFG_OFFSET;
183
184 /* CP110 revision A2 or CN913x */
185 if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2 ||
186 cp110_device_id_get(base) == MVEBU_CN9130_DEV_ID) {
187 /*
188 * PCIe Reference Clock Buffer Control register must be
189 * set according to the clock direction (input/output)
190 */
191 reg = mmio_read_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL);
192 reg &= ~(PCIE0_REFCLK_BUFF_SOURCE | PCIE1_REFCLK_BUFF_SOURCE);
193 if (!pcie0_clk)
194 reg |= PCIE0_REFCLK_BUFF_SOURCE;
195 if (!pcie1_clk)
196 reg |= PCIE1_REFCLK_BUFF_SOURCE;
197
198 mmio_write_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL, reg);
199 }
200
201 /* CP110 revision A1 */
202 if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A1) {
203 if (!pcie0_clk || !pcie1_clk) {
204 /*
205 * if one of the pcie clocks is set to input,
206 * we need to set mss_push[131] field, otherwise,
207 * the pcie clock might not work.
208 */
209 reg = mmio_read_32(base + MVEBU_CP_MSS_DPSHSR_REG);
210 reg |= MSS_DPSHSR_REG_PCIE_CLK_SEL;
211 mmio_write_32(base + MVEBU_CP_MSS_DPSHSR_REG, reg);
212 }
213 }
214 }
215
216 /* Set a unique stream id for all DMA capable devices */
cp110_stream_id_init(uintptr_t base,uint32_t stream_id)217 static void cp110_stream_id_init(uintptr_t base, uint32_t stream_id)
218 {
219 int i = 0;
220
221 while (stream_id_reg[i]) {
222 if (i > MAX_STREAM_ID_PER_CP) {
223 NOTICE("Only first %d (maximum) Stream IDs allocated\n",
224 MAX_STREAM_ID_PER_CP);
225 return;
226 }
227
228 if ((stream_id_reg[i] == CP_DMA_0_STREAM_ID_REG) ||
229 (stream_id_reg[i] == CP_DMA_1_STREAM_ID_REG))
230 mmio_write_32(base + stream_id_reg[i],
231 stream_id << 16 | stream_id);
232 else
233 mmio_write_32(base + stream_id_reg[i], stream_id);
234
235 /* SATA port 0/1 are in the same SATA unit, and they should use
236 * the same STREAM ID number
237 */
238 if (stream_id_reg[i] != SATA_0_STREAM_ID_REG)
239 stream_id++;
240
241 i++;
242 }
243 }
244
cp110_axi_attr_init(uintptr_t base)245 static void cp110_axi_attr_init(uintptr_t base)
246 {
247 uint32_t index, data;
248
249 /* Initialize AXI attributes for Armada-7K/8K SoC */
250
251 /* Go over the AXI attributes and set Ax-Cache and Ax-Domain */
252 for (index = 0; index < AXI_MAX_ATTR; index++) {
253 switch (index) {
254 /* DFX and MSS unit works with no coherent only -
255 * there's no option to configure the Ax-Cache and Ax-Domain
256 */
257 case AXI_DFX_ATTR:
258 case AXI_MSS_ATTR:
259 continue;
260 default:
261 /* Set Ax-Cache as cacheable, no allocate, modifiable,
262 * bufferable
263 * The values are different because Read & Write
264 * definition is different in Ax-Cache
265 */
266 data = mmio_read_32(base + MVEBU_AXI_ATTR_REG(index));
267 data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK;
268 data |= (CACHE_ATTR_WRITE_ALLOC |
269 CACHE_ATTR_CACHEABLE |
270 CACHE_ATTR_BUFFERABLE) <<
271 MVEBU_AXI_ATTR_ARCACHE_OFFSET;
272 data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK;
273 data |= (CACHE_ATTR_READ_ALLOC |
274 CACHE_ATTR_CACHEABLE |
275 CACHE_ATTR_BUFFERABLE) <<
276 MVEBU_AXI_ATTR_AWCACHE_OFFSET;
277 /* Set Ax-Domain as Outer domain */
278 data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK;
279 data |= DOMAIN_OUTER_SHAREABLE <<
280 MVEBU_AXI_ATTR_ARDOMAIN_OFFSET;
281 data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK;
282 data |= DOMAIN_OUTER_SHAREABLE <<
283 MVEBU_AXI_ATTR_AWDOMAIN_OFFSET;
284 mmio_write_32(base + MVEBU_AXI_ATTR_REG(index), data);
285 }
286 }
287
288 /* SATA IOCC supported, cache attributes
289 * for SATA MBUS to AXI configuration.
290 */
291 data = mmio_read_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG);
292 data &= ~MVEBU_SATA_M2A_AXI_AWCACHE_MASK;
293 data |= (CACHE_ATTR_WRITE_ALLOC |
294 CACHE_ATTR_CACHEABLE |
295 CACHE_ATTR_BUFFERABLE) <<
296 MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET;
297 data &= ~MVEBU_SATA_M2A_AXI_ARCACHE_MASK;
298 data |= (CACHE_ATTR_READ_ALLOC |
299 CACHE_ATTR_CACHEABLE |
300 CACHE_ATTR_BUFFERABLE) <<
301 MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET;
302 mmio_write_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG, data);
303
304 /* Set all IO's AXI attribute to non-secure access. */
305 for (index = 0; index < MVEBU_AXI_PROT_REGS_NUM; index++)
306 mmio_write_32(base + MVEBU_AXI_PROT_REG(index),
307 DOMAIN_SYSTEM_SHAREABLE);
308 }
309
cp110_amb_init(uintptr_t base)310 void cp110_amb_init(uintptr_t base)
311 {
312 uint32_t reg;
313
314 /* Open AMB bridge Window to Access COMPHY/MDIO registers */
315 reg = mmio_read_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0));
316 reg &= ~(MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK |
317 MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK);
318 reg |= (0x7ff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET) |
319 (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET);
320 mmio_write_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0), reg);
321 }
322
cp110_rtc_init(uintptr_t base)323 static void cp110_rtc_init(uintptr_t base)
324 {
325 /* Update MBus timing parameters before accessing RTC registers */
326 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG,
327 MVEBU_RTC_WRCLK_PERIOD_MASK,
328 MVEBU_RTC_WRCLK_PERIOD_DEFAULT);
329
330 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG,
331 MVEBU_RTC_WRCLK_SETUP_MASK,
332 MVEBU_RTC_WRCLK_SETUP_DEFAULT <<
333 MVEBU_RTC_WRCLK_SETUP_OFFS);
334
335 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG,
336 MVEBU_RTC_READ_OUTPUT_DELAY_MASK,
337 MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT);
338
339 /*
340 * Issue reset to the RTC if Clock Correction register
341 * contents did not sustain the reboot/power-on.
342 */
343 if ((mmio_read_32(base + MVEBU_RTC_CCR_REG) &
344 MVEBU_RTC_NOMINAL_TIMING_MASK) != MVEBU_RTC_NOMINAL_TIMING) {
345 /* Reset Test register */
346 mmio_write_32(base + MVEBU_RTC_TEST_CONFIG_REG, 0);
347 mdelay(500);
348
349 /* Reset Status register */
350 mmio_write_32(base + MVEBU_RTC_STATUS_REG,
351 (MVEBU_RTC_STATUS_ALARM1_MASK |
352 MVEBU_RTC_STATUS_ALARM2_MASK));
353 udelay(62);
354
355 /* Turn off Int1 and Int2 sources & clear the Alarm count */
356 mmio_write_32(base + MVEBU_RTC_IRQ_1_CONFIG_REG, 0);
357 mmio_write_32(base + MVEBU_RTC_IRQ_2_CONFIG_REG, 0);
358 mmio_write_32(base + MVEBU_RTC_ALARM_1_REG, 0);
359 mmio_write_32(base + MVEBU_RTC_ALARM_2_REG, 0);
360
361 /* Setup nominal register access timing */
362 mmio_write_32(base + MVEBU_RTC_CCR_REG,
363 MVEBU_RTC_NOMINAL_TIMING);
364
365 /* Reset Status register */
366 mmio_write_32(base + MVEBU_RTC_STATUS_REG,
367 (MVEBU_RTC_STATUS_ALARM1_MASK |
368 MVEBU_RTC_STATUS_ALARM2_MASK));
369 udelay(50);
370 }
371 }
372
cp110_amb_adec_init(uintptr_t base)373 static void cp110_amb_adec_init(uintptr_t base)
374 {
375 /* enable AXI-MBUS by clearing "Bridge Windows Disable" */
376 mmio_clrbits_32(base + MVEBU_BRIDGE_WIN_DIS_REG,
377 (1 << MVEBU_BRIDGE_WIN_DIS_OFF));
378
379 /* configure AXI-MBUS windows for CP */
380 init_amb_adec(base);
381 }
382
cp110_init(uintptr_t cp110_base,uint32_t stream_id)383 void cp110_init(uintptr_t cp110_base, uint32_t stream_id)
384 {
385 INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base);
386
387 /* configure IOB windows for CP0*/
388 init_iob(cp110_base);
389
390 /* configure AXI-MBUS windows for CP0*/
391 cp110_amb_adec_init(cp110_base);
392
393 /* configure axi for CP0*/
394 cp110_axi_attr_init(cp110_base);
395
396 /* Execute SW WA for erratas */
397 cp110_errata_wa_init(cp110_base);
398
399 /* Confiure pcie clock according to clock direction */
400 cp110_pcie_clk_cfg(cp110_base);
401
402 /* configure stream id for CP0 */
403 cp110_stream_id_init(cp110_base, stream_id);
404
405 /* Open AMB bridge for comphy for CP0 & CP1*/
406 cp110_amb_init(cp110_base);
407
408 /* Reset RTC if needed */
409 cp110_rtc_init(cp110_base);
410 }
411
412 /* Do the minimal setup required to configure the CP in BLE */
cp110_ble_init(uintptr_t cp110_base)413 void cp110_ble_init(uintptr_t cp110_base)
414 {
415 #if PCI_EP_SUPPORT
416 INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base);
417
418 cp110_amb_init(cp110_base);
419
420 /* Configure PCIe clock */
421 cp110_pcie_clk_cfg(cp110_base);
422
423 /* Configure PCIe endpoint */
424 ble_plat_pcie_ep_setup();
425 #endif
426 }
427