1 /*
2 * Copyright 2022, 2025 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <arch.h>
10 #include <caam.h>
11 #include <cci.h>
12 #include <common/debug.h>
13 #include <dcfg.h>
14 #ifdef I2C_INIT
15 #include <i2c.h>
16 #endif
17 #include <lib/mmio.h>
18 #include <lib/xlat_tables/xlat_tables_v2.h>
19 #include <ls_interconnect.h>
20 #include <nxp_smmu.h>
21 #include <nxp_timer.h>
22 #include <plat_console.h>
23 #include <plat_gic.h>
24 #include <plat_tzc400.h>
25 #include <pmu.h>
26 #if defined(NXP_SFP_ENABLED)
27 #include <sfp.h>
28 #endif
29 #if TRUSTED_BOARD_BOOT
30 #include <snvs.h>
31 #endif
32
33 #include <errata.h>
34 #ifdef CONFIG_OCRAM_ECC_EN
35 #include <ocram.h>
36 #endif
37 #include <plat_common.h>
38 #include <platform_def.h>
39 #include <soc.h>
40
41 static unsigned char _power_domain_tree_desc[NUMBER_OF_CLUSTERS + 2];
42 static struct soc_type soc_list[] = {
43 SOC_ENTRY(LS1044A, LS1044A, 1, 4),
44 SOC_ENTRY(LS1044AE, LS1044AE, 1, 4),
45 SOC_ENTRY(LS1048A, LS1048A, 1, 4),
46 SOC_ENTRY(LS1048AE, LS1048AE, 1, 4),
47 SOC_ENTRY(LS1084A, LS1084A, 2, 4),
48 SOC_ENTRY(LS1084AE, LS1084AE, 2, 4),
49 SOC_ENTRY(LS1088A, LS1088A, 2, 4),
50 SOC_ENTRY(LS1088AE, LS1088AE, 2, 4),
51 };
52
53 static dcfg_init_info_t dcfg_init_data = {
54 .g_nxp_dcfg_addr = NXP_DCFG_ADDR,
55 .nxp_sysclk_freq = NXP_SYSCLK_FREQ,
56 .nxp_ddrclk_freq = NXP_DDRCLK_FREQ,
57 .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER,
58 };
59
60 /*
61 * This function dynamically constructs the topology according to
62 * SoC Flavor and returns it.
63 */
plat_get_power_domain_tree_desc(void)64 const unsigned char *plat_get_power_domain_tree_desc(void)
65 {
66 unsigned int i;
67 uint8_t num_clusters, cores_per_cluster;
68
69 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
70
71 /*
72 * The highest level is the system level. The next level is constituted
73 * by clusters and then cores in clusters.
74 */
75 _power_domain_tree_desc[0] = 1;
76 _power_domain_tree_desc[1] = num_clusters;
77
78 for (i = 0; i < _power_domain_tree_desc[1]; i++) {
79 _power_domain_tree_desc[i + 2] = cores_per_cluster;
80 }
81
82
83 return _power_domain_tree_desc;
84 }
85
86 CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256,
87 assert_invalid_ls1088a_cluster_count);
88
89 /*
90 * This function returns the core count within the cluster corresponding to
91 * `mpidr`.
92 */
plat_ls_get_cluster_core_count(u_register_t mpidr)93 unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
94 {
95 return CORES_PER_CLUSTER;
96 }
97
98 /*
99 * This function returns the total number of cores in the SoC
100 */
get_tot_num_cores(void)101 unsigned int get_tot_num_cores(void)
102 {
103 uint8_t num_clusters, cores_per_cluster;
104
105 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
106
107 return (num_clusters * cores_per_cluster);
108 }
109
110 /*
111 * This function returns the PMU IDLE Cluster mask.
112 */
get_pmu_idle_cluster_mask(void)113 unsigned int get_pmu_idle_cluster_mask(void)
114 {
115 uint8_t num_clusters, cores_per_cluster;
116
117 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
118
119 return ((1 << num_clusters) - 2);
120 }
121
122 /*
123 * This function returns the PMU Flush Cluster mask.
124 */
get_pmu_flush_cluster_mask(void)125 unsigned int get_pmu_flush_cluster_mask(void)
126 {
127 uint8_t num_clusters, cores_per_cluster;
128
129 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
130
131 return ((1 << num_clusters) - 2);
132 }
133
134 /*
135 * This function returns the PMU IDLE Core mask.
136 */
get_pmu_idle_core_mask(void)137 unsigned int get_pmu_idle_core_mask(void)
138 {
139 return ((1 << get_tot_num_cores()) - 2);
140 }
141
142 #ifdef IMAGE_BL2
143
soc_bl2_prepare_exit(void)144 void soc_bl2_prepare_exit(void)
145 {
146 #if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE)
147 set_sfp_wr_disable();
148 #endif
149 }
150
soc_preload_setup(void)151 void soc_preload_setup(void)
152 {
153
154 }
155
156 /*
157 * This function returns the boot device based on RCW_SRC
158 */
get_boot_dev(void)159 enum boot_device get_boot_dev(void)
160 {
161 enum boot_device src = BOOT_DEVICE_NONE;
162 uint32_t porsr1;
163 uint32_t rcw_src, val;
164
165 porsr1 = read_reg_porsr1();
166
167 rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT;
168
169 /* RCW SRC NOR */
170 val = rcw_src & RCW_SRC_TYPE_MASK;
171 if (val == NOR_16B_VAL) {
172 src = BOOT_DEVICE_IFC_NOR;
173 INFO("RCW BOOT SRC is IFC NOR\n");
174 } else {
175 val = rcw_src & RCW_SRC_SERIAL_MASK;
176 switch (val) {
177 case QSPI_VAL:
178 src = BOOT_DEVICE_QSPI;
179 INFO("RCW BOOT SRC is QSPI\n");
180 break;
181 case SDHC_VAL:
182 src = BOOT_DEVICE_EMMC;
183 INFO("RCW BOOT SRC is SD/EMMC\n");
184 break;
185 case EMMC_VAL:
186 src = BOOT_DEVICE_EMMC;
187 INFO("RCW BOOT SRC is SD/EMMC\n");
188 break;
189 default:
190 src = BOOT_DEVICE_NONE;
191 }
192 }
193
194 return src;
195 }
196
197 /*
198 * This function sets up access permissions on memory regions
199 */
soc_mem_access(void)200 void soc_mem_access(void)
201 {
202 dram_regions_info_t *info_dram_regions = get_dram_regions_info();
203 int i = 0;
204 struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION];
205 int dram_idx, index = 1;
206
207 for (dram_idx = 0; dram_idx < info_dram_regions->num_dram_regions;
208 dram_idx++) {
209 if (info_dram_regions->region[i].size == 0) {
210 ERROR("DDR init failure, or");
211 ERROR("DRAM regions not populated correctly.\n");
212 break;
213 }
214
215 index = populate_tzc400_reg_list(tzc400_reg_list,
216 dram_idx, index,
217 info_dram_regions->region[dram_idx].addr,
218 info_dram_regions->region[dram_idx].size,
219 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE);
220 }
221
222 mem_access_setup(NXP_TZC_ADDR, index,
223 tzc400_reg_list);
224 }
225
226 /*
227 * This function implements soc specific erratum
228 * This is called before DDR is initialized or MMU is enabled
229 */
soc_early_init(void)230 void soc_early_init(void)
231 {
232 enum boot_device dev;
233 dram_regions_info_t *dram_regions_info = get_dram_regions_info();
234
235 #if TRUSTED_BOARD_BOOT
236 snvs_init(NXP_SNVS_ADDR);
237 #endif
238
239 #ifdef CONFIG_OCRAM_ECC_EN
240 ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE);
241 #endif
242 dcfg_init(&dcfg_init_data);
243 #if LOG_LEVEL > 0
244 /* Initialize the console to provide early debug support */
245 plat_console_init(NXP_CONSOLE_ADDR,
246 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
247 #endif
248 enable_timer_base_to_cluster(NXP_PMU_ADDR);
249 enable_core_tb(NXP_PMU_ADDR);
250
251 /*
252 * Use the region(NXP_SD_BLOCK_BUF_ADDR + NXP_SD_BLOCK_BUF_SIZE)
253 * as dma of sd
254 */
255 dev = get_boot_dev();
256 if (dev == BOOT_DEVICE_EMMC) {
257 mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR,
258 NXP_SD_BLOCK_BUF_SIZE,
259 MT_DEVICE | MT_RW | MT_NS);
260 }
261
262 /*
263 * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
264 */
265 smmu_cache_unlock(NXP_SMMU_ADDR);
266 INFO("SMMU Cache Unlocking is Configured.\n");
267
268 #if TRUSTED_BOARD_BOOT
269 uint32_t mode;
270
271 sfp_init(NXP_SFP_ADDR);
272 /*
273 * For secure boot disable SMMU.
274 * Later when platform security policy comes in picture,
275 * this might get modified based on the policy
276 */
277 if (check_boot_mode_secure(&mode) == true) {
278 bypass_smmu(NXP_SMMU_ADDR);
279 }
280
281 /*
282 * For Mbedtls currently crypto is not supported via CAAM
283 * enable it when that support is there. In tbbr.mk
284 * the CAAM_INTEG is set as 0.
285 */
286 #ifndef MBEDTLS_X509
287 /* Initialize the crypto accelerator if enabled */
288 if (is_sec_enabled() == false) {
289 INFO("SEC is disabled.\n");
290 } else {
291 sec_init(NXP_CAAM_ADDR);
292 }
293 #endif
294 #endif
295
296 soc_errata();
297
298 delay_timer_init(NXP_TIMER_ADDR);
299 i2c_init(NXP_I2C_ADDR);
300 dram_regions_info->total_dram_size = init_ddr();
301 }
302 #else /* !IMAGE_BL2 */
303
soc_early_platform_setup2(void)304 void soc_early_platform_setup2(void)
305 {
306 dcfg_init(&dcfg_init_data);
307 /*
308 * Initialize system level generic timer for Socs
309 */
310 delay_timer_init(NXP_TIMER_ADDR);
311
312 #if LOG_LEVEL > 0
313 /* Initialize the console to provide early debug support */
314 plat_console_init(NXP_CONSOLE_ADDR,
315 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
316 #endif
317 }
318
soc_platform_setup(void)319 void soc_platform_setup(void)
320 {
321 /* Initialize the GIC driver, cpu and distributor interfaces */
322 static uintptr_t target_mask_array[PLATFORM_CORE_COUNT];
323 static interrupt_prop_t ls_interrupt_props[] = {
324 PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S),
325 PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0)
326 };
327
328 plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR,
329 PLATFORM_CORE_COUNT,
330 ls_interrupt_props,
331 ARRAY_SIZE(ls_interrupt_props),
332 target_mask_array,
333 plat_core_pos);
334
335 plat_ls_gic_init();
336 enable_init_timer();
337 }
338
339 /*
340 * This function initializes the soc from the BL31 module
341 */
soc_init(void)342 void soc_init(void)
343 {
344 uint8_t num_clusters, cores_per_cluster;
345
346 /* low-level init of the soc */
347 soc_init_lowlevel();
348 _init_global_data();
349 soc_init_percpu();
350 _initialize_psci();
351
352 /*
353 * Initialize Interconnect for this cluster during cold boot.
354 * No need for locks as no other CPU is active.
355 */
356 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
357
358 /*
359 * Enable Interconnect coherency for the primary CPU's cluster.
360 */
361 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
362 plat_ls_interconnect_enter_coherency(num_clusters);
363
364 /* set platform security policies */
365 _set_platform_security();
366
367 /* Initialize the crypto accelerator if enabled */
368 if (is_sec_enabled() == false) {
369 INFO("SEC is disabled.\n");
370 } else {
371 sec_init(NXP_CAAM_ADDR);
372 }
373 }
374
soc_runtime_setup(void)375 void soc_runtime_setup(void)
376 {
377
378 }
379 #endif /* IMAGE_BL2 */
380
381 /*
382 * Function to return the SoC SYS CLK
383 */
get_sys_clk(void)384 unsigned int get_sys_clk(void)
385 {
386 return NXP_SYSCLK_FREQ;
387 }
388
389 /*
390 * Function returns the base counter frequency
391 * after reading the first entry at CNTFID0 (0x20 offset).
392 *
393 * Function is used by:
394 * 1. ARM common code for PSCI management.
395 * 2. ARM Generic Timer init.
396 */
plat_get_syscnt_freq2(void)397 unsigned int plat_get_syscnt_freq2(void)
398 {
399 unsigned int counter_base_frequency;
400 /*
401 * Below register specifies the base frequency of the system counter.
402 * As per NXP Board Manuals:
403 * The system counter always works with SYS_REF_CLK/4 frequency clock.
404 */
405 counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF);
406
407 return counter_base_frequency;
408 }
409