1*d4e6f98dSHope Wang /*
2*d4e6f98dSHope Wang * Copyright (c) 2025, Mediatek Inc. All rights reserved.
3*d4e6f98dSHope Wang *
4*d4e6f98dSHope Wang * SPDX-License-Identifier: BSD-3-Clause
5*d4e6f98dSHope Wang */
6*d4e6f98dSHope Wang
7*d4e6f98dSHope Wang #include <errno.h>
8*d4e6f98dSHope Wang
9*d4e6f98dSHope Wang #include <common/debug.h>
10*d4e6f98dSHope Wang #include <drivers/pmic/pmic_set_lowpower.h>
11*d4e6f98dSHope Wang #include <drivers/pmic/pmic_swap_api.h>
12*d4e6f98dSHope Wang #include <drivers/spmi/spmi_common.h>
13*d4e6f98dSHope Wang #include <lib/mtk_init/mtk_init.h>
14*d4e6f98dSHope Wang
15*d4e6f98dSHope Wang #define MASTER_ID SPMI_MASTER_1
16*d4e6f98dSHope Wang
17*d4e6f98dSHope Wang struct spmi_device *lowpower_sdev[SPMI_MAX_SLAVE_ID];
18*d4e6f98dSHope Wang
19*d4e6f98dSHope Wang static const uint8_t lowpower_slvid_arr[] = {
20*d4e6f98dSHope Wang MT6363_SLAVE,
21*d4e6f98dSHope Wang MT6373_SLAVE,
22*d4e6f98dSHope Wang MT6316_S6_SLAVE,
23*d4e6f98dSHope Wang MT6316_S7_SLAVE,
24*d4e6f98dSHope Wang MT6316_S8_SLAVE,
25*d4e6f98dSHope Wang MT6316_S15_SLAVE,
26*d4e6f98dSHope Wang };
27*d4e6f98dSHope Wang
pmic_lowpower_init(void)28*d4e6f98dSHope Wang static int pmic_lowpower_init(void)
29*d4e6f98dSHope Wang {
30*d4e6f98dSHope Wang uint8_t i, slvid;
31*d4e6f98dSHope Wang
32*d4e6f98dSHope Wang for (i = 0; i < ARRAY_SIZE(lowpower_slvid_arr); i++) {
33*d4e6f98dSHope Wang slvid = lowpower_slvid_arr[i];
34*d4e6f98dSHope Wang lowpower_sdev[slvid] = get_spmi_device(MASTER_ID, slvid);
35*d4e6f98dSHope Wang if (!lowpower_sdev[slvid])
36*d4e6f98dSHope Wang return -ENODEV;
37*d4e6f98dSHope Wang }
38*d4e6f98dSHope Wang
39*d4e6f98dSHope Wang /* MT6363 Deep idle, SODI3 */
40*d4e6f98dSHope Wang /* VREQ config by SCP owner in LK2 */
41*d4e6f98dSHope Wang PMIC_BUCK_SET_LP(MT6363, VBUCK4, HW2, true, OP_MODE_LP, HW_LP);
42*d4e6f98dSHope Wang PMIC_BUCK_SET_LP(MT6363, VBUCK4, RC9, true, OP_MODE_MU, HW_ON);
43*d4e6f98dSHope Wang PMIC_BUCK_SET_LP(MT6363, VS2, HW2, true, OP_MODE_LP, HW_LP);
44*d4e6f98dSHope Wang PMIC_BUCK_SET_LP(MT6363, VS2, RC9, true, OP_MODE_MU, HW_ON);
45*d4e6f98dSHope Wang PMIC_BUCK_SET_LP(MT6363, VS3, HW2, true, OP_MODE_LP, HW_LP);
46*d4e6f98dSHope Wang PMIC_LDO_SET_LP(MT6363, VSRAM_CPUB, HW2, true, OP_MODE_LP, HW_LP);
47*d4e6f98dSHope Wang PMIC_LDO_SET_LP(MT6363, VSRAM_CPUB, RC9, true, OP_MODE_MU, HW_ON);
48*d4e6f98dSHope Wang PMIC_LDO_SET_LP(MT6363, VSRAM_CPUL, HW2, true, OP_MODE_LP, HW_LP);
49*d4e6f98dSHope Wang PMIC_LDO_SET_LP(MT6363, VSRAM_CPUL, RC9, true, OP_MODE_MU, HW_ON);
50*d4e6f98dSHope Wang PMIC_LDO_SET_LP(MT6363, VSRAM_APU, RC2, true, OP_MODE_MU, HW_OFF);
51*d4e6f98dSHope Wang PMIC_LDO_SET_LP(MT6363, VSRAM_MODEM, HW2, true, OP_MODE_LP, HW_LP);
52*d4e6f98dSHope Wang PMIC_LDO_SET_LP(MT6363, VSRAM_MODEM, RC9, true, OP_MODE_MU, HW_ON);
53*d4e6f98dSHope Wang PMIC_LDO_SET_LP(MT6363, VA12_1, HW2, true, OP_MODE_LP, HW_LP);
54*d4e6f98dSHope Wang PMIC_LDO_SET_LP(MT6363, VA12_1, RC9, true, OP_MODE_MU, HW_ON);
55*d4e6f98dSHope Wang PMIC_LDO_SET_LP(MT6363, VA12_2, HW2, true, OP_MODE_LP, HW_LP);
56*d4e6f98dSHope Wang PMIC_LDO_SET_LP(MT6363, VA12_2, RC9, true, OP_MODE_MU, HW_ON);
57*d4e6f98dSHope Wang PMIC_LDO_SET_LP(MT6363, VUFS18, HW2, true, OP_MODE_LP, HW_LP);
58*d4e6f98dSHope Wang PMIC_LDO_SET_LP(MT6363, VUFS18, RC9, true, OP_MODE_MU, HW_ON);
59*d4e6f98dSHope Wang PMIC_LDO_SET_LP(MT6363, VUFS12, HW2, true, OP_MODE_LP, HW_LP);
60*d4e6f98dSHope Wang
61*d4e6f98dSHope Wang /* MT6373 Deep idle, SODI3 */
62*d4e6f98dSHope Wang PMIC_BUCK_SET_LP(MT6373, VBUCK4, HW2, true, OP_MODE_LP, HW_OFF);
63*d4e6f98dSHope Wang PMIC_BUCK_SET_LP(MT6373, VBUCK5, HW2, true, OP_MODE_LP, HW_OFF);
64*d4e6f98dSHope Wang PMIC_BUCK_SET_LP(MT6373, VBUCK6, HW2, true, OP_MODE_LP, HW_LP);
65*d4e6f98dSHope Wang PMIC_LDO_SET_LP(MT6373, VUSB, HW2, true, OP_MODE_LP, HW_LP);
66*d4e6f98dSHope Wang
67*d4e6f98dSHope Wang /* MT6316 Deep idle, SODI3 */
68*d4e6f98dSHope Wang PMIC_SLVID_BUCK_SET_LP(MT6316, S8, VBUCK1, HW2, true, OP_MODE_LP, HW_LP);
69*d4e6f98dSHope Wang PMIC_SLVID_BUCK_SET_LP(MT6316, S6, VBUCK3, HW2, true, OP_MODE_LP, HW_ONLV);
70*d4e6f98dSHope Wang return 0;
71*d4e6f98dSHope Wang }
72*d4e6f98dSHope Wang
73*d4e6f98dSHope Wang MTK_PLAT_SETUP_0_INIT(pmic_lowpower_init);
74