| #
02711885 |
| 28-Oct-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): refactor SDMMC driver for Altera products" into integration
|
| #
beba2040 |
| 25-Oct-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): refactor SDMMC driver for Altera products
Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.
Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
S
fix(intel): refactor SDMMC driver for Altera products
Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.
Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
show more ...
|
| #
97d48be0 |
| 30-Aug-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): update memcpy to memcpy_s" into integration
|
| #
e264b557 |
| 25-Aug-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): update memcpy to memcpy_s
memcpy does not check the dst_size which may
create vulnerable issue as it can overflow the buffer.
Using memcpy_s which check the dst_size will help to
reduce
fix(intel): update memcpy to memcpy_s
memcpy does not check the dst_size which may
create vulnerable issue as it can overflow the buffer.
Using memcpy_s which check the dst_size will help to
reduce the risk. Also, this memcpy is always 4 bytes
each time.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I413e6ae2ee9330501703c4cd63b7943c6f55b4c7
show more ...
|
| #
3393060c |
| 06-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "agilex5" into integration
* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for A
Merge changes from topic "agilex5" into integration
* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for Agilex5 SoC FPGA
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
feat(intel): ddr driver for Agilex5 SoC FPGA
feat(intel): power manager for Agilex5 SoC FPGA
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
feat(intel): reset manager support for Agilex5 SoC FPGA
feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
feat(intel): system manager support for Agilex5 SoC FPGA
feat(intel): memory controller support for Agilex5 SoC FPGA
feat(intel): clock manager support for Agilex5 SoC FPGA
feat(intel): mmc support for Agilex5 SoC FPGA
feat(intel): uart support for Agilex5 SoC FPGA
feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA
show more ...
|
| #
ddaf02d1 |
| 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-PHY support.
2. Updated product name -> Agilex5
3. Updated QSPI base address
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6
show more ...
|