Home
last modified time | relevance | path

Searched +full:zynqmp +full:- +full:8 (Results 1 – 25 of 54) sorted by relevance

123

/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1232-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZC1232
5 * (C) Copyright 2017 - 2019, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP ZC1232 RevA";
17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
26 stdout-path = "serial0:115200n8";
42 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
[all …]
H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
17 model = "ZynqMP zc1751-xm015-dc1 RevA";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
31 stdout-path = "serial0:115200n8";
[all …]
H A Dzynqmp-zc1751-xm017-dc3.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3
5 * (C) Copyright 2016 - 2019, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm017-dc3 RevA";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
31 stdout-path = "serial0:115200n8";
74 phy-handle = <&phy0>;
[all …]
H A Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2019, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
17 model = "ZynqMP ZCU104 RevA";
18 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
32 stdout-path = "serial0:115200n8";
[all …]
H A Dzynqmp-zc1751-xm018-dc4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
116 phy-mode = "rgmii-id";
[all …]
H A Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
18 model = "ZynqMP zc1751-xm019-dc5 RevA";
19 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
32 stdout-path = "serial0:115200n8";
[all …]
H A Dzynqmp-zcu100-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU100 revC
5 * (C) Copyright 2016 - 2019, Xilinx, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/gpio/gpio.h>
20 model = "ZynqMP ZCU100 RevC";
[all …]
H A Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU111
5 * (C) Copyright 2017 - 2019, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
18 model = "ZynqMP ZCU111 RevA";
19 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
[all …]
H A Dzynqmp-zcu106-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU106
5 * (C) Copyright 2016 - 2019, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
18 model = "ZynqMP ZCU106 RevA";
19 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
[all …]
H A Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU102 RevA
5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
18 model = "ZynqMP ZCU102 RevA";
19 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dzynqmp-zc1751-xm015-dc1.dts2 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
8 * SPDX-License-Identifier: GPL-2.0+
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk.dtsi"
17 model = "ZynqMP zc1751-xm015-dc1 RevA";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
46 xlnx,include-sg; /* for testing purpose */
49 xlnx,src-issue = <31>;
[all …]
H A Dzynqmp-zc1751-xm018-dc4.dts2 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
4 * (C) Copyright 2015 - 2016, Xilinx, Inc.
14 /dts-v1/;
16 #include "zynqmp.dtsi"
17 #include "zynqmp-clk.dtsi"
20 model = "ZynqMP zc1751-xm018-dc4";
21 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
41 stdout-path = "serial0:115200n8";
61 xlnx,include-sg; /* for testing purpose */
64 xlnx,src-issue = <31>;
[all …]
H A Dzynqmp-ep108.dts2 * dts file for Xilinx ZynqMP ep108 development board
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
8 * SPDX-License-Identifier: GPL-2.0+
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-ep108-clk.dtsi"
17 model = "ZynqMP EP108";
32 stdout-path = "serial0:115200n8";
51 phy-handle = <&phy0>;
52 phy-mode = "rgmii-id";
[all …]
H A Dzynqmp-zc1751-xm016-dc2.dts2 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
8 * SPDX-License-Identifier: GPL-2.0+
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk.dtsi"
17 model = "ZynqMP zc1751-xm016-dc2 RevA";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
36 stdout-path = "serial0:115200n8";
56 xlnx,include-sg; /* for testing purpose */
59 xlnx,src-issue = <31>;
[all …]
H A Dzynqmp.dtsi2 * dts file for Xilinx ZynqMP
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
8 * SPDX-License-Identifier: GPL-2.0+
12 compatible = "xlnx,zynqmp";
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-a53", "arm,armv8";
23 enable-method = "psci";
[all …]
H A Dzynqmp-zcu102-revA.dts2 * dts file for Xilinx ZynqMP ZCU102
8 * SPDX-License-Identifier: GPL-2.0+
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
18 model = "ZynqMP ZCU102 RevA";
19 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
37 stdout-path = "serial0:115200n8";
45 gpio-keys {
[all …]
/OK3568_Linux_fs/kernel/drivers/dma/xilinx/
H A Dzynqmp_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DMA driver for Xilinx ZynqMP DMA Engine
21 #include <linux/io-64-nonatomic-lo-hi.h>
56 #define ZYNQMP_DMA_AXI_RD_DATA BIT(8)
82 #define ZYNQMP_DMA_AWCACHE GENMASK(11, 8)
83 #define ZYNQMP_DMA_AWCACHE_OFST 8
90 #define ZYNQMP_DMA_AXCOHRNT BIT(8)
143 #define ZYNQMP_DMA_DESC_SIZE(chan) (chan->desc_size)
151 * struct zynqmp_dma_desc_ll - Hw linked list descriptor
167 * struct zynqmp_dma_desc_sw - Per Transaction structure
[all …]
/OK3568_Linux_fs/buildroot/board/zynqmp/patches/uboot/
H A D0003-arm64-zynqmp-accept-an-absolute-path-for-PMUFW_INIT_.patch4 Subject: [PATCH] arm64: zynqmp: accept an absolute path for PMUFW_INIT_FILE
7 forcing it to be a relative path inside the U-Boot source tree. Since
8 the PMUFW is a binary file generated outside of U-Boot, the PMUFW
9 binary must be copied inside the U-Boot source tree before the
14 * if the source tree is shared among different out-of-tree builds,
16 * the source tree cannot be read-only
18 * putting an externally-generated binary in the source tree is ugly
27 Since 'readlink -f' produces an empty string if the file does not
33 - PMUFW_INIT_FILE empty, relative, absolute, non-existing
34 - building in-tree, in subdir, in other directory
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/xlnx/
H A Dzynqmp_dpsub.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP DisplayPort Subsystem Driver
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 #include <linux/dma-mapping.h>
35 /* -----------------------------------------------------------------------------
44 unsigned int pitch = DIV_ROUND_UP(args->width * args->bpp, 8); in zynqmp_dpsub_dumb_create()
47 args->pitch = ALIGN(pitch, dpsub->dma_align); in zynqmp_dpsub_dumb_create()
62 cmd.pitches[i] = ALIGN(cmd.pitches[i], dpsub->dma_align); in zynqmp_dpsub_fb_create()
[all …]
/OK3568_Linux_fs/kernel/Documentation/driver-api/xilinx/
H A Deemi.rst6 -------------------------------------
7 The zynqmp-firmware node describes the interface to platform firmware.
8 ZynqMP has an interface to communicate with secure firmware. Firmware
13 ----------------------------------------------
23 ------
30 - IOCTL_SET_PLL_FRAC_MODE 8
31 - IOCTL_GET_PLL_FRAC_MODE 9
32 - IOCTL_SET_PLL_FRAC_DATA 10
33 - IOCTL_GET_PLL_FRAC_DATA 11
38 ----------
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: "mmc-controller.yaml#"
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/
H A DKconfig20 stand-alone devices. Useful in particular for systems that support
21 DM_ETH and have a stand-alone MDIO hardware block shared by multiple
23 This is currently implemented in net/mdio-uclass.c
61 bool "Altera Triple-Speed Ethernet MAC support"
65 This driver supports the Altera Triple-Speed (TSE) Ethernet MAC.
66 Please find details on the "Triple-Speed Ethernet MegaCore Function
143 U-Boot.
161 in U-Boot to the RAW AF_PACKET API in Linux. This allows real
191 bool "Marvell Armada 375/7K/8K network interface support"
196 Marvell ARMADA 375, 7K and 8K SoCs.
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
75 #define STEP_SIZE_SHIFT 8
158 #define XPSGTR_TYPE_DP_0 8 /* Display Port controller lane 0 */
171 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
185 * struct xpsgtr_phy - representation of a lane
205 * struct xpsgtr_dev - representation of a ZynMP GT device
[all …]
/OK3568_Linux_fs/u-boot/drivers/usb/host/
H A Dxhci-zynqmp.c10 * SPDX-License-Identifier: GPL-2.0+
25 /* Default to the ZYNQMP XHCI defines */
53 #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8)
75 ret = dwc3_core_init(zynqmp_xhci->dwc3_reg); in zynqmp_xhci_core_init()
81 /* We are hard-coding DWC3 core to Host Mode */ in zynqmp_xhci_core_init()
82 dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); in zynqmp_xhci_core_init()
90 * Currently zynqmp socs do not support PHY shutdown from in xhci_hcd_stop()
104 ctx->hcd = (struct xhci_hccr *)plat->hcd_base; in xhci_usb_probe()
105 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); in xhci_usb_probe()
110 return -EINVAL; in xhci_usb_probe()
[all …]
/OK3568_Linux_fs/buildroot/boot/uboot/
H A DConfig.in2 bool "U-Boot"
4 Build "Das U-Boot" Boot Monitor
6 https://www.denx.de/wiki/U-Boot
17 Select this option if you use a recent U-Boot version (2015.04
23 Select this option if you use an old U-Boot (older than
30 string "U-Boot board name"
32 One of U-Boot supported boards to be built.
33 This will be suffixed with _config to meet U-Boot standard
34 naming. See boards.cfg in U-Boot source code for the list of
39 prompt "U-Boot Version"
[all …]

123