1/* 2 * dts file for Xilinx ZynqMP ep108 development board 3 * 4 * (C) Copyright 2014 - 2015, Xilinx, Inc. 5 * 6 * Michal Simek <michal.simek@xilinx.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11/dts-v1/; 12 13#include "zynqmp.dtsi" 14#include "zynqmp-ep108-clk.dtsi" 15 16/ { 17 model = "ZynqMP EP108"; 18 19 aliases { 20 mmc0 = &sdhci0; 21 mmc1 = &sdhci1; 22 serial0 = &uart0; 23 spi0 = &qspi; 24 spi1 = &spi0; 25 spi2 = &spi1; 26 usb0 = &usb0; 27 usb1 = &usb1; 28 }; 29 30 chosen { 31 bootargs = "earlycon"; 32 stdout-path = "serial0:115200n8"; 33 }; 34 35 memory@0 { 36 device_type = "memory"; 37 reg = <0x0 0x0 0x0 0x40000000>; 38 }; 39}; 40 41&can0 { 42 status = "okay"; 43}; 44 45&can1 { 46 status = "okay"; 47}; 48 49&gem0 { 50 status = "okay"; 51 phy-handle = <&phy0>; 52 phy-mode = "rgmii-id"; 53 phy0: phy@0 { 54 reg = <0>; 55 max-speed = <100>; 56 }; 57}; 58 59&gpio { 60 status = "okay"; 61}; 62 63&i2c0 { 64 status = "okay"; 65 clock-frequency = <400000>; 66 eeprom@54 { 67 compatible = "at,24c64"; 68 reg = <0x54>; 69 }; 70}; 71 72&i2c1 { 73 status = "okay"; 74 clock-frequency = <400000>; 75 eeprom@55 { 76 compatible = "at,24c64"; 77 reg = <0x55>; 78 }; 79}; 80 81&nand0 { 82 status = "okay"; 83 arasan,has-mdma; 84 num-cs = <1>; 85 86 partition@0 { /* for testing purpose */ 87 label = "nand-fsbl-uboot"; 88 reg = <0x0 0x0 0x400000>; 89 }; 90 partition@1 { /* for testing purpose */ 91 label = "nand-linux"; 92 reg = <0x0 0x400000 0x1400000>; 93 }; 94 partition@2 { /* for testing purpose */ 95 label = "nand-device-tree"; 96 reg = <0x0 0x1800000 0x400000>; 97 }; 98 partition@3 { /* for testing purpose */ 99 label = "nand-rootfs"; 100 reg = <0x0 0x1C00000 0x1400000>; 101 }; 102 partition@4 { /* for testing purpose */ 103 label = "nand-bitstream"; 104 reg = <0x0 0x3000000 0x400000>; 105 }; 106 partition@5 { /* for testing purpose */ 107 label = "nand-misc"; 108 reg = <0x0 0x3400000 0xFCC00000>; 109 }; 110}; 111 112&qspi { 113 status = "okay"; 114 flash@0 { 115 compatible = "m25p80"; 116 #address-cells = <1>; 117 #size-cells = <1>; 118 reg = <0x0>; 119 spi-tx-bus-width = <1>; 120 spi-rx-bus-width = <4>; 121 spi-max-frequency = <10000000>; 122 partition@qspi-fsbl-uboot { /* for testing purpose */ 123 label = "qspi-fsbl-uboot"; 124 reg = <0x0 0x100000>; 125 }; 126 partition@qspi-linux { /* for testing purpose */ 127 label = "qspi-linux"; 128 reg = <0x100000 0x500000>; 129 }; 130 partition@qspi-device-tree { /* for testing purpose */ 131 label = "qspi-device-tree"; 132 reg = <0x600000 0x20000>; 133 }; 134 partition@qspi-rootfs { /* for testing purpose */ 135 label = "qspi-rootfs"; 136 reg = <0x620000 0x5E0000>; 137 }; 138 }; 139}; 140 141&sata { 142 status = "okay"; 143 ceva,broken-gen2; 144 /* SATA Phy OOB timing settings */ 145 ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; 146 ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; 147 ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; 148 ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>; 149 ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; 150 ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; 151 ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; 152 ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>; 153}; 154 155&sdhci0 { 156 status = "okay"; 157 bus-width = <8>; 158 xlnx,mio_bank = <2>; 159}; 160 161&sdhci1 { 162 status = "okay"; 163 xlnx,mio_bank = <1>; 164}; 165 166&spi0 { 167 status = "okay"; 168 num-cs = <1>; 169 spi0_flash0: spi0_flash0@0 { 170 compatible = "m25p80"; 171 #address-cells = <1>; 172 #size-cells = <1>; 173 spi-max-frequency = <50000000>; 174 reg = <0>; 175 176 spi0_flash0@00000000 { 177 label = "spi0_flash0"; 178 reg = <0x0 0x100000>; 179 }; 180 }; 181}; 182 183&spi1 { 184 status = "okay"; 185 num-cs = <1>; 186 spi1_flash0: spi1_flash0@0 { 187 compatible = "m25p80"; 188 #address-cells = <1>; 189 #size-cells = <1>; 190 spi-max-frequency = <50000000>; 191 reg = <0>; 192 193 spi1_flash0@00000000 { 194 label = "spi1_flash0"; 195 reg = <0x0 0x100000>; 196 }; 197 }; 198}; 199 200&uart0 { 201 status = "okay"; 202}; 203 204&usb0 { 205 status = "okay"; 206}; 207 208&dwc3_0 { 209 status = "okay"; 210 dr_mode = "peripheral"; 211 maximum-speed = "high-speed"; 212}; 213 214&usb1 { 215 status = "okay"; 216}; 217 218&dwc3_1 { 219 status = "okay"; 220 dr_mode = "host"; 221 maximum-speed = "high-speed"; 222}; 223 224&watchdog0 { 225 status = "okay"; 226}; 227 228&xlnx_dp { 229 xlnx,max-pclock-frequency = <200000>; 230}; 231 232&xlnx_dpdma { 233 xlnx,axi-clock-freq = <200000000>; 234}; 235