xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * dts file for Xilinx ZynqMP ZCU104
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (C) Copyright 2017 - 2019, Xilinx, Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/dts-v1/;
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun#include "zynqmp.dtsi"
13*4882a593Smuzhiyun#include "zynqmp-clk-ccf.dtsi"
14*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun/ {
17*4882a593Smuzhiyun	model = "ZynqMP ZCU104 RevA";
18*4882a593Smuzhiyun	compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	aliases {
21*4882a593Smuzhiyun		ethernet0 = &gem3;
22*4882a593Smuzhiyun		i2c0 = &i2c1;
23*4882a593Smuzhiyun		mmc0 = &sdhci1;
24*4882a593Smuzhiyun		rtc0 = &rtc;
25*4882a593Smuzhiyun		serial0 = &uart0;
26*4882a593Smuzhiyun		serial1 = &uart1;
27*4882a593Smuzhiyun		serial2 = &dcc;
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	chosen {
31*4882a593Smuzhiyun		bootargs = "earlycon";
32*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun	memory@0 {
36*4882a593Smuzhiyun		device_type = "memory";
37*4882a593Smuzhiyun		reg = <0x0 0x0 0x0 0x80000000>;
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun&can1 {
42*4882a593Smuzhiyun	status = "okay";
43*4882a593Smuzhiyun};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun&dcc {
46*4882a593Smuzhiyun	status = "okay";
47*4882a593Smuzhiyun};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun&gem3 {
50*4882a593Smuzhiyun	status = "okay";
51*4882a593Smuzhiyun	phy-handle = <&phy0>;
52*4882a593Smuzhiyun	phy-mode = "rgmii-id";
53*4882a593Smuzhiyun	phy0: ethernet-phy@c {
54*4882a593Smuzhiyun		reg = <0xc>;
55*4882a593Smuzhiyun		ti,rx-internal-delay = <0x8>;
56*4882a593Smuzhiyun		ti,tx-internal-delay = <0xa>;
57*4882a593Smuzhiyun		ti,fifo-depth = <0x1>;
58*4882a593Smuzhiyun		ti,dp83867-rxctrl-strap-quirk;
59*4882a593Smuzhiyun	};
60*4882a593Smuzhiyun};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun&gpio {
63*4882a593Smuzhiyun	status = "okay";
64*4882a593Smuzhiyun};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun&i2c1 {
67*4882a593Smuzhiyun	status = "okay";
68*4882a593Smuzhiyun	clock-frequency = <400000>;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	/* Another connection to this bus via PL i2c via PCA9306 - u45 */
71*4882a593Smuzhiyun	i2c-mux@74 { /* u34 */
72*4882a593Smuzhiyun		compatible = "nxp,pca9548";
73*4882a593Smuzhiyun		#address-cells = <1>;
74*4882a593Smuzhiyun		#size-cells = <0>;
75*4882a593Smuzhiyun		reg = <0x74>;
76*4882a593Smuzhiyun		i2c@0 {
77*4882a593Smuzhiyun			#address-cells = <1>;
78*4882a593Smuzhiyun			#size-cells = <0>;
79*4882a593Smuzhiyun			reg = <0>;
80*4882a593Smuzhiyun			/*
81*4882a593Smuzhiyun			 * IIC_EEPROM 1kB memory which uses 256B blocks
82*4882a593Smuzhiyun			 * where every block has different address.
83*4882a593Smuzhiyun			 *    0 - 256B address 0x54
84*4882a593Smuzhiyun			 * 256B - 512B address 0x55
85*4882a593Smuzhiyun			 * 512B - 768B address 0x56
86*4882a593Smuzhiyun			 * 768B - 1024B address 0x57
87*4882a593Smuzhiyun			 */
88*4882a593Smuzhiyun			eeprom@54 { /* u23 */
89*4882a593Smuzhiyun				compatible = "atmel,24c08";
90*4882a593Smuzhiyun				reg = <0x54>;
91*4882a593Smuzhiyun				#address-cells = <1>;
92*4882a593Smuzhiyun				#size-cells = <1>;
93*4882a593Smuzhiyun			};
94*4882a593Smuzhiyun		};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun		i2c@1 {
97*4882a593Smuzhiyun			#address-cells = <1>;
98*4882a593Smuzhiyun			#size-cells = <0>;
99*4882a593Smuzhiyun			reg = <1>;
100*4882a593Smuzhiyun			clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
101*4882a593Smuzhiyun				reg = <0x6c>;
102*4882a593Smuzhiyun			};
103*4882a593Smuzhiyun		};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun		i2c@2 {
106*4882a593Smuzhiyun			#address-cells = <1>;
107*4882a593Smuzhiyun			#size-cells = <0>;
108*4882a593Smuzhiyun			reg = <2>;
109*4882a593Smuzhiyun			irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
110*4882a593Smuzhiyun				reg = <0x43>;
111*4882a593Smuzhiyun			};
112*4882a593Smuzhiyun			irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
113*4882a593Smuzhiyun				reg = <0x4d>;
114*4882a593Smuzhiyun			};
115*4882a593Smuzhiyun		};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun		i2c@4 {
118*4882a593Smuzhiyun			#address-cells = <1>;
119*4882a593Smuzhiyun			#size-cells = <0>;
120*4882a593Smuzhiyun			reg = <4>;
121*4882a593Smuzhiyun			tca6416_u97: gpio@20 {
122*4882a593Smuzhiyun				compatible = "ti,tca6416";
123*4882a593Smuzhiyun				reg = <0x20>;
124*4882a593Smuzhiyun				gpio-controller;
125*4882a593Smuzhiyun				#gpio-cells = <2>;
126*4882a593Smuzhiyun				/*
127*4882a593Smuzhiyun				 * IRQ not connected
128*4882a593Smuzhiyun				 * Lines:
129*4882a593Smuzhiyun				 * 0 - IRPS5401_ALERT_B
130*4882a593Smuzhiyun				 * 1 - HDMI_8T49N241_INT_ALM
131*4882a593Smuzhiyun				 * 2 - MAX6643_OT_B
132*4882a593Smuzhiyun				 * 3 - MAX6643_FANFAIL_B
133*4882a593Smuzhiyun				 * 5 - IIC_MUX_RESET_B
134*4882a593Smuzhiyun				 * 6 - GEM3_EXP_RESET_B
135*4882a593Smuzhiyun				 * 7 - FMC_LPC_PRSNT_M2C_B
136*4882a593Smuzhiyun				 * 4, 10 - 17 - not connected
137*4882a593Smuzhiyun				 */
138*4882a593Smuzhiyun			};
139*4882a593Smuzhiyun		};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun		i2c@5 {
142*4882a593Smuzhiyun			#address-cells = <1>;
143*4882a593Smuzhiyun			#size-cells = <0>;
144*4882a593Smuzhiyun			reg = <5>;
145*4882a593Smuzhiyun		};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun		i2c@7 {
148*4882a593Smuzhiyun			#address-cells = <1>;
149*4882a593Smuzhiyun			#size-cells = <0>;
150*4882a593Smuzhiyun			reg = <7>;
151*4882a593Smuzhiyun		};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun		/* 3, 6 not connected */
154*4882a593Smuzhiyun	};
155*4882a593Smuzhiyun};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun&rtc {
158*4882a593Smuzhiyun	status = "okay";
159*4882a593Smuzhiyun};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun&sata {
162*4882a593Smuzhiyun	status = "okay";
163*4882a593Smuzhiyun	/* SATA OOB timing settings */
164*4882a593Smuzhiyun	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
165*4882a593Smuzhiyun	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
166*4882a593Smuzhiyun	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
167*4882a593Smuzhiyun	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
168*4882a593Smuzhiyun	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
169*4882a593Smuzhiyun	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
170*4882a593Smuzhiyun	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
171*4882a593Smuzhiyun	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
172*4882a593Smuzhiyun};
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun/* SD1 with level shifter */
175*4882a593Smuzhiyun&sdhci1 {
176*4882a593Smuzhiyun	status = "okay";
177*4882a593Smuzhiyun	no-1-8-v;
178*4882a593Smuzhiyun	disable-wp;
179*4882a593Smuzhiyun};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun&uart0 {
182*4882a593Smuzhiyun	status = "okay";
183*4882a593Smuzhiyun};
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun&uart1 {
186*4882a593Smuzhiyun	status = "okay";
187*4882a593Smuzhiyun};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun/* ULPI SMSC USB3320 */
190*4882a593Smuzhiyun&usb0 {
191*4882a593Smuzhiyun	status = "okay";
192*4882a593Smuzhiyun	dr_mode = "host";
193*4882a593Smuzhiyun};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun&watchdog0 {
196*4882a593Smuzhiyun	status = "okay";
197*4882a593Smuzhiyun};
198