1 /*
2 * Copyright 2015 Xilinx, Inc.
3 *
4 * Zynq USB HOST xHCI Controller
5 *
6 * Author: Siva Durga Prasad Paladugu<sivadur@xilinx.com>
7 *
8 * This file was reused from Freescale USB xHCI
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13 #include <common.h>
14 #include <dm.h>
15 #include <usb.h>
16 #include <linux/errno.h>
17 #include <asm/arch/hardware.h>
18 #include <linux/compat.h>
19 #include <linux/usb/dwc3.h>
20 #include "xhci.h"
21
22 /* Declare global data pointer */
23 DECLARE_GLOBAL_DATA_PTR;
24
25 /* Default to the ZYNQMP XHCI defines */
26 #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
27 #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
28 #define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
29 #define USB3_PHY_RX_POWERON BIT(14)
30 #define USB3_PHY_TX_POWERON BIT(15)
31 #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
32 #define USB3_PWRCTL_CLK_CMD_SHIFT 14
33 #define USB3_PWRCTL_CLK_FREQ_SHIFT 22
34
35 /* USBOTGSS_WRAPPER definitions */
36 #define USBOTGSS_WRAPRESET BIT(17)
37 #define USBOTGSS_DMADISABLE BIT(16)
38 #define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4)
39 #define USBOTGSS_STANDBYMODE_SMRT BIT(5)
40 #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
41 #define USBOTGSS_IDLEMODE_NOIDLE BIT(2)
42 #define USBOTGSS_IDLEMODE_SMRT BIT(3)
43 #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
44
45 /* USBOTGSS_IRQENABLE_SET_0 bit */
46 #define USBOTGSS_COREIRQ_EN BIT(1)
47
48 /* USBOTGSS_IRQENABLE_SET_1 bits */
49 #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1)
50 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3)
51 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4)
52 #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5)
53 #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8)
54 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11)
55 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12)
56 #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13)
57 #define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16)
58 #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17)
59
60 struct zynqmp_xhci {
61 struct usb_platdata usb_plat;
62 struct xhci_ctrl ctrl;
63 struct xhci_hccr *hcd;
64 struct dwc3 *dwc3_reg;
65 };
66
67 struct zynqmp_xhci_platdata {
68 fdt_addr_t hcd_base;
69 };
70
zynqmp_xhci_core_init(struct zynqmp_xhci * zynqmp_xhci)71 static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci)
72 {
73 int ret = 0;
74
75 ret = dwc3_core_init(zynqmp_xhci->dwc3_reg);
76 if (ret) {
77 debug("%s:failed to initialize core\n", __func__);
78 return ret;
79 }
80
81 /* We are hard-coding DWC3 core to Host Mode */
82 dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
83
84 return ret;
85 }
86
xhci_hcd_stop(int index)87 void xhci_hcd_stop(int index)
88 {
89 /*
90 * Currently zynqmp socs do not support PHY shutdown from
91 * sw. But this support may be added in future socs.
92 */
93
94 return;
95 }
96
xhci_usb_probe(struct udevice * dev)97 static int xhci_usb_probe(struct udevice *dev)
98 {
99 struct zynqmp_xhci_platdata *plat = dev_get_platdata(dev);
100 struct zynqmp_xhci *ctx = dev_get_priv(dev);
101 struct xhci_hcor *hcor;
102 int ret;
103
104 ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
105 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
106
107 ret = zynqmp_xhci_core_init(ctx);
108 if (ret) {
109 puts("XHCI: failed to initialize controller\n");
110 return -EINVAL;
111 }
112
113 hcor = (struct xhci_hcor *)((ulong)ctx->hcd +
114 HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
115
116 return xhci_register(dev, ctx->hcd, hcor);
117 }
118
xhci_usb_remove(struct udevice * dev)119 static int xhci_usb_remove(struct udevice *dev)
120 {
121 return xhci_deregister(dev);
122 }
123
xhci_usb_ofdata_to_platdata(struct udevice * dev)124 static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
125 {
126 struct zynqmp_xhci_platdata *plat = dev_get_platdata(dev);
127 const void *blob = gd->fdt_blob;
128
129 /* Get the base address for XHCI controller from the device node */
130 plat->hcd_base = fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
131 if (plat->hcd_base == FDT_ADDR_T_NONE) {
132 debug("Can't get the XHCI register base address\n");
133 return -ENXIO;
134 }
135
136 return 0;
137 }
138
139 U_BOOT_DRIVER(dwc3_generic_host) = {
140 .name = "dwc3-generic-host",
141 .id = UCLASS_USB,
142 .ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
143 .probe = xhci_usb_probe,
144 .remove = xhci_usb_remove,
145 .ops = &xhci_usb_ops,
146 .platdata_auto_alloc_size = sizeof(struct zynqmp_xhci_platdata),
147 .priv_auto_alloc_size = sizeof(struct zynqmp_xhci),
148 .flags = DM_FLAG_ALLOC_PRIV_DMA,
149 };
150