xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * dts file for Xilinx ZynqMP zc1751-xm017-dc3
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (C) Copyright 2016 - 2019, Xilinx, Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/dts-v1/;
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun#include "zynqmp.dtsi"
13*4882a593Smuzhiyun#include "zynqmp-clk-ccf.dtsi"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun/ {
16*4882a593Smuzhiyun	model = "ZynqMP zc1751-xm017-dc3 RevA";
17*4882a593Smuzhiyun	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	aliases {
20*4882a593Smuzhiyun		ethernet0 = &gem0;
21*4882a593Smuzhiyun		i2c0 = &i2c0;
22*4882a593Smuzhiyun		i2c1 = &i2c1;
23*4882a593Smuzhiyun		mmc0 = &sdhci1;
24*4882a593Smuzhiyun		rtc0 = &rtc;
25*4882a593Smuzhiyun		serial0 = &uart0;
26*4882a593Smuzhiyun		serial1 = &uart1;
27*4882a593Smuzhiyun	};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun	chosen {
30*4882a593Smuzhiyun		bootargs = "earlycon";
31*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
32*4882a593Smuzhiyun	};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun	memory@0 {
35*4882a593Smuzhiyun		device_type = "memory";
36*4882a593Smuzhiyun		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
37*4882a593Smuzhiyun	};
38*4882a593Smuzhiyun};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun&fpd_dma_chan1 {
41*4882a593Smuzhiyun	status = "okay";
42*4882a593Smuzhiyun};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun&fpd_dma_chan2 {
45*4882a593Smuzhiyun	status = "okay";
46*4882a593Smuzhiyun};
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun&fpd_dma_chan3 {
49*4882a593Smuzhiyun	status = "okay";
50*4882a593Smuzhiyun};
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun&fpd_dma_chan4 {
53*4882a593Smuzhiyun	status = "okay";
54*4882a593Smuzhiyun};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun&fpd_dma_chan5 {
57*4882a593Smuzhiyun	status = "okay";
58*4882a593Smuzhiyun};
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun&fpd_dma_chan6 {
61*4882a593Smuzhiyun	status = "okay";
62*4882a593Smuzhiyun};
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun&fpd_dma_chan7 {
65*4882a593Smuzhiyun	status = "okay";
66*4882a593Smuzhiyun};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun&fpd_dma_chan8 {
69*4882a593Smuzhiyun	status = "okay";
70*4882a593Smuzhiyun};
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun&gem0 {
73*4882a593Smuzhiyun	status = "okay";
74*4882a593Smuzhiyun	phy-handle = <&phy0>;
75*4882a593Smuzhiyun	phy-mode = "rgmii-id";
76*4882a593Smuzhiyun	phy0: ethernet-phy@0 { /* VSC8211 */
77*4882a593Smuzhiyun		reg = <0>;
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun&gpio {
82*4882a593Smuzhiyun	status = "okay";
83*4882a593Smuzhiyun};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun/* just eeprom here */
86*4882a593Smuzhiyun&i2c0 {
87*4882a593Smuzhiyun	status = "okay";
88*4882a593Smuzhiyun	clock-frequency = <400000>;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun	tca6416_u26: gpio@20 {
91*4882a593Smuzhiyun		compatible = "ti,tca6416";
92*4882a593Smuzhiyun		reg = <0x20>;
93*4882a593Smuzhiyun		gpio-controller;
94*4882a593Smuzhiyun		#gpio-cells = <2>;
95*4882a593Smuzhiyun		/* IRQ not connected */
96*4882a593Smuzhiyun	};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun	rtc@68 {
99*4882a593Smuzhiyun		compatible = "dallas,ds1339";
100*4882a593Smuzhiyun		reg = <0x68>;
101*4882a593Smuzhiyun	};
102*4882a593Smuzhiyun};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun/* eeprom24c02 and SE98A temp chip pca9306 */
105*4882a593Smuzhiyun&i2c1 {
106*4882a593Smuzhiyun	status = "okay";
107*4882a593Smuzhiyun	clock-frequency = <400000>;
108*4882a593Smuzhiyun};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun&rtc {
111*4882a593Smuzhiyun	status = "okay";
112*4882a593Smuzhiyun};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun&sata {
115*4882a593Smuzhiyun	status = "okay";
116*4882a593Smuzhiyun	/* SATA phy OOB timing settings */
117*4882a593Smuzhiyun	ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
118*4882a593Smuzhiyun	ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
119*4882a593Smuzhiyun	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
120*4882a593Smuzhiyun	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
121*4882a593Smuzhiyun	ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
122*4882a593Smuzhiyun	ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
123*4882a593Smuzhiyun	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
124*4882a593Smuzhiyun	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
125*4882a593Smuzhiyun};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun&sdhci1 { /* emmc with some settings */
128*4882a593Smuzhiyun	status = "okay";
129*4882a593Smuzhiyun};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun/* main */
132*4882a593Smuzhiyun&uart0 {
133*4882a593Smuzhiyun	status = "okay";
134*4882a593Smuzhiyun};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun/* DB9 */
137*4882a593Smuzhiyun&uart1 {
138*4882a593Smuzhiyun	status = "okay";
139*4882a593Smuzhiyun};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun&usb0 {
142*4882a593Smuzhiyun	status = "okay";
143*4882a593Smuzhiyun	dr_mode = "host";
144*4882a593Smuzhiyun};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun/* ULPI SMSC USB3320 */
147*4882a593Smuzhiyun&usb1 {
148*4882a593Smuzhiyun	status = "okay";
149*4882a593Smuzhiyun	dr_mode = "host";
150*4882a593Smuzhiyun};
151