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/OK3568_Linux_fs/kernel/sound/drivers/
H A Dserial-u16550.c159 static inline void snd_uart16550_add_timer(struct snd_uart16550 *uart) in snd_uart16550_add_timer() argument
161 if (!uart->timer_running) { in snd_uart16550_add_timer()
163 mod_timer(&uart->buffer_timer, jiffies + (HZ + 255) / 256); in snd_uart16550_add_timer()
164 uart->timer_running = 1; in snd_uart16550_add_timer()
168 static inline void snd_uart16550_del_timer(struct snd_uart16550 *uart) in snd_uart16550_del_timer() argument
170 if (uart->timer_running) { in snd_uart16550_del_timer()
171 del_timer(&uart->buffer_timer); in snd_uart16550_del_timer()
172 uart->timer_running = 0; in snd_uart16550_del_timer()
177 static inline void snd_uart16550_buffer_output(struct snd_uart16550 *uart) in snd_uart16550_buffer_output() argument
179 unsigned short buff_out = uart->buff_out; in snd_uart16550_buffer_output()
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/OK3568_Linux_fs/u-boot/drivers/serial/
H A DKconfig12 meaning of either setting the baudrate for the early debug UART
32 In very space-constrained devices even the full UART driver is too
33 large. In this case the debug UART can still be used in some cases.
34 This option enables the full UART in U-Boot, so if is it disabled,
35 the full UART driver will be omitted, thus saving space.
42 In very space-constrained devices even the full UART driver is too
43 large. In this case the debug UART can still be used in some cases.
44 This option enables the full UART in SPL, so if is it disabled,
45 the full UART driver will be omitted, thus saving space.
48 int "UART used for console"
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H A Dmcfuart.c12 * Minimal serial functions needed to use one of the uart ports
22 #include <asm/uart.h>
28 static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate) in mcf_serial_init_common() argument
34 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ in mcf_serial_init_common()
35 writeb(UART_UCR_RESET_RX, &uart->ucr); in mcf_serial_init_common()
36 writeb(UART_UCR_RESET_TX, &uart->ucr); in mcf_serial_init_common()
37 writeb(UART_UCR_RESET_ERROR, &uart->ucr); in mcf_serial_init_common()
38 writeb(UART_UCR_RESET_MR, &uart->ucr); in mcf_serial_init_common()
41 writeb(0, &uart->uimr); in mcf_serial_init_common()
44 writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); in mcf_serial_init_common()
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H A Dserial_s5p.c18 #include <asm/arch/uart.h>
34 u8 port_id; /* uart port number */
63 static void __maybe_unused s5p_serial_init(struct s5p_uart *uart) in s5p_serial_init() argument
66 writel(0x3, &uart->ufcon); in s5p_serial_init()
67 writel(0, &uart->umcon); in s5p_serial_init()
69 writel(0x3, &uart->ulcon); in s5p_serial_init()
71 writel(0x245, &uart->ucon); in s5p_serial_init()
74 static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, uint uclk, in s5p_serial_baud() argument
81 writel(val / 16 - 1, &uart->ubrdiv); in s5p_serial_baud()
84 writew(udivslot[val % 16], &uart->rest.slot); in s5p_serial_baud()
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H A Dserial_pxa.c25 #include <asm/arch/regs-uart.h>
79 /* Enable UART */ in pxa_setbrg_common()
103 panic("Failed getting UART registers\n"); in pxa_setbrg_dev()
178 #define pxa_uart(uart, UART) \ argument
179 int uart##_init(void) \
181 return pxa_init_dev(UART##_INDEX); \
184 void uart##_setbrg(void) \
186 return pxa_setbrg_dev(UART##_INDEX); \
189 void uart##_putc(const char c) \
191 return pxa_putc_dev(UART##_INDEX, c); \
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/OK3568_Linux_fs/kernel/drivers/tty/serial/
H A Dmen_z135_uart.c3 * MEN 16z135 High Speed UART
132 * @uart: The UART port
136 static inline void men_z135_reg_set(struct men_z135_port *uart, in men_z135_reg_set() argument
139 struct uart_port *port = &uart->port; in men_z135_reg_set()
143 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_set()
149 spin_unlock_irqrestore(&uart->lock, flags); in men_z135_reg_set()
154 * @uart: The UART port
158 static void men_z135_reg_clr(struct men_z135_port *uart, in men_z135_reg_clr() argument
161 struct uart_port *port = &uart->port; in men_z135_reg_clr()
165 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_clr()
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H A Dtimbuart.c3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
55 struct timbuart_port *uart = in timbuart_start_tx() local
59 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
121 struct timbuart_port *uart = in timbuart_handle_tx_port() local
140 *ier |= uart->last_ier & TXFLAGS; in timbuart_handle_tx_port()
177 struct timbuart_port *uart = from_tasklet(uart, t, tasklet); in timbuart_tasklet() local
180 spin_lock(&uart->port.lock); in timbuart_tasklet()
182 isr = ioread32(uart->port.membase + TIMBUART_ISR); in timbuart_tasklet()
183 dev_dbg(uart->port.dev, "%s ISR: %x\n", __func__, isr); in timbuart_tasklet()
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H A Darc_uart.c3 * ARC On-Chip(fpga) UART Driver
17 * -New Serial Core based ARC UART driver
37 * ARC UART Hardware Specs
42 * UART Register set (this is not a Standards Compliant IP)
54 /* Bits for UART Status Reg (R/W) */
67 /* Uart bit fiddling helpers: lowest level */
75 /* Uart bit fiddling helpers: API level */
76 #define UART_SET_DATA(uart, val) UART_REG_SET(uart, R_DATA, val) argument
77 #define UART_GET_DATA(uart) UART_REG_GET(uart, R_DATA) argument
79 #define UART_SET_BAUDH(uart, val) UART_REG_SET(uart, R_BAUDH, val) argument
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/serial/
H A Dfsl-imx-uart.yaml4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
19 - const: fsl,imx1-uart
20 - const: fsl,imx21-uart
23 - fsl,imx25-uart
24 - fsl,imx27-uart
25 - fsl,imx31-uart
26 - fsl,imx35-uart
27 - fsl,imx50-uart
28 - fsl,imx51-uart
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H A Dmvebu-uart.txt1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
6 - "marvell,armada-3700-uart" for the standard variant of the UART
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
20 (marvell,armada-3700-uart): "uart-sum", "uart-tx" and "uart-rx",
21 respectively the UART sum interrupt, the UART TX interrupt and
22 UART RX interrupt. A corresponding interrupt-names property must
25 (marvell,armada-3700-uart-ext): "uart-tx" and "uart-rx",
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H A Dmtk-uart.txt1 * MediaTek Universal Asynchronous Receiver/Transmitter (UART)
5 * "mediatek,mt2701-uart" for MT2701 compatible UARTS
6 * "mediatek,mt2712-uart" for MT2712 compatible UARTS
7 * "mediatek,mt6580-uart" for MT6580 compatible UARTS
8 * "mediatek,mt6582-uart" for MT6582 compatible UARTS
9 * "mediatek,mt6589-uart" for MT6589 compatible UARTS
10 * "mediatek,mt6755-uart" for MT6755 compatible UARTS
11 * "mediatek,mt6765-uart" for MT6765 compatible UARTS
12 * "mediatek,mt6779-uart" for MT6779 compatible UARTS
13 * "mediatek,mt6795-uart" for MT6795 compatible UARTS
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H A Dsnps-dw-apb-uart.yaml4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
7 title: Synopsys DesignWare ABP UART
20 - renesas,r9a06g032-uart
21 - renesas,r9a06g033-uart
22 - const: renesas,rzn1-uart
25 - rockchip,px30-uart
26 - rockchip,rk3036-uart
27 - rockchip,rk3066-uart
28 - rockchip,rk3188-uart
29 - rockchip,rk3288-uart
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H A D8250.yaml7 title: UART (Universal Asynchronous Receiver/Transmitter) bindings
24 const: mrvl,mmp-uart
56 - const: intel,xscale-uart
57 - const: mrvl,pxa-uart
58 - const: nuvoton,npcm750-uart
59 - const: nvidia,tegra20-uart
60 - const: nxp,lpc3220-uart
69 - nxp,lpc1850-uart
71 - ti,da830-uart
76 - cavium,octeon-3860-uart
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H A Dsamsung_uart.yaml7 title: Samsung S3C, S5P and Exynos SoC UART Controller
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
22 - samsung,s3c2410-uart
23 - samsung,s3c2412-uart
24 - samsung,s3c2440-uart
25 - samsung,s3c6400-uart
26 - samsung,s5pv210-uart
27 - samsung,exynos4210-uart
48 - const: uart
59 samsung,uart-fifosize:
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H A Dsirf-uart.txt4 - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
5 "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
7 - interrupts : Should contain uart interrupt
9 - clocks : Should contain uart clock number
12 - uart-has-rtscts: we have hardware flow controller pins in hardware
13 - rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true
14 - cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true
18 uart0: uart@b0050000 {
20 compatible = "sirf,prima2-uart";
30 compatible = "sirf,prima2-usp-uart";
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/OK3568_Linux_fs/kernel/drivers/tty/serial/8250/
H A D8250_core.c287 * IIR bits on their UART, but it's specifically designed for in serial8250_backup_timeout()
288 * the "Diva" UART used on the management processor on many HP in serial8250_backup_timeout()
601 * Check whether an invalid uart number has been specified, and in univ8250_console_setup()
633 * console=uart[8250],io|mmio|mmio16|mmio32,<addr>[,<options>]
634 * console=uart[8250],0x<addr>[,<options>]
646 char match[] = "uart"; /* 8250-specific earlycon name */ in univ8250_console_match()
815 struct uart_8250_port uart; in serial8250_probe() local
818 memset(&uart, 0, sizeof(uart)); in serial8250_probe()
824 uart.port.iobase = p->iobase; in serial8250_probe()
825 uart.port.membase = p->membase; in serial8250_probe()
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H A D8250_tegra.c44 struct tegra_uart *uart; in tegra_uart_probe() local
49 uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL); in tegra_uart_probe()
50 if (!uart) in tegra_uart_probe()
89 uart->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); in tegra_uart_probe()
90 if (IS_ERR(uart->rst)) in tegra_uart_probe()
91 return PTR_ERR(uart->rst); in tegra_uart_probe()
95 uart->clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
96 if (IS_ERR(uart->clk)) { in tegra_uart_probe()
101 ret = clk_prepare_enable(uart->clk); in tegra_uart_probe()
105 port->uartclk = clk_get_rate(uart->clk); in tegra_uart_probe()
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H A D8250_ingenic.c6 * Ingenic SoC UART support
132 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
135 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
138 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
141 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
144 OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
153 /* UART module enable */ in ingenic_uart_serial_out()
209 struct uart_8250_port uart = {}; in ingenic_uart_probe() local
237 spin_lock_init(&uart.port.lock); in ingenic_uart_probe()
238 uart.port.type = PORT_16550A; in ingenic_uart_probe()
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H A D8250_lpc18xx.c3 * Serial port driver for NXP LPC18xx/43xx UART
104 struct uart_8250_port uart; in lpc18xx_serial_probe() local
118 memset(&uart, 0, sizeof(uart)); in lpc18xx_serial_probe()
120 uart.port.membase = devm_ioremap(&pdev->dev, res->start, in lpc18xx_serial_probe()
122 if (!uart.port.membase) in lpc18xx_serial_probe()
131 dev_err(&pdev->dev, "uart clock not found\n"); in lpc18xx_serial_probe()
149 dev_err(&pdev->dev, "unable to enable uart clock\n"); in lpc18xx_serial_probe()
155 uart.port.line = ret; in lpc18xx_serial_probe()
160 spin_lock_init(&uart.port.lock); in lpc18xx_serial_probe()
161 uart.port.dev = &pdev->dev; in lpc18xx_serial_probe()
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H A D8250_pxa.c57 { .compatible = "mrvl,pxa-uart", },
58 { .compatible = "mrvl,mmp-uart", },
63 /* Uart divisor latch write */
93 struct uart_8250_port uart = {}; in serial_pxa_probe() local
120 uart.port.line = ret; in serial_pxa_probe()
122 uart.port.type = PORT_XSCALE; in serial_pxa_probe()
123 uart.port.iotype = UPIO_MEM32; in serial_pxa_probe()
124 uart.port.mapbase = mmres->start; in serial_pxa_probe()
125 uart.port.regshift = 2; in serial_pxa_probe()
126 uart.port.irq = irq; in serial_pxa_probe()
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/OK3568_Linux_fs/kernel/arch/mips/kernel/
H A Dcps-vec-ns16550.S32 * _mips_cps_putc() - write a character to the UART
34 * @t9: UART base address
45 * _mips_cps_puts() - write a string to the UART
47 * @t9: UART base address
49 * Write a null-terminated ASCII string to the UART.
65 * _mips_cps_putx4 - write a 4b hex value to the UART
66 * @a0: the 4b value to write to the UART
67 * @t9: UART base address
69 * Write a single hexadecimal character to the UART.
82 * _mips_cps_putx8 - write an 8b hex value to the UART
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/OK3568_Linux_fs/u-boot/board/astro/mcf5373l/
H A Dmcf5373l.c17 #include <asm/uart.h>
91 uart_t *uart; in rs_serial_init() local
96 uart = (uart_t *)(MMAP_UART0); in rs_serial_init()
99 uart = (uart_t *)(MMAP_UART1); in rs_serial_init()
102 uart = (uart_t *)(MMAP_UART2); in rs_serial_init()
105 uart = (uart_t *)(MMAP_UART0); in rs_serial_init()
110 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ in rs_serial_init()
111 writeb(UART_UCR_RESET_RX, &uart->ucr); in rs_serial_init()
112 writeb(UART_UCR_RESET_TX, &uart->ucr); in rs_serial_init()
113 writeb(UART_UCR_RESET_ERROR, &uart->ucr); in rs_serial_init()
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/OK3568_Linux_fs/kernel/arch/arm/include/debug/
H A Dtegra.S45 #define checkuart(rp, rv, lhu, bit, uart) \ argument
50 /* Test UART's reset bit */ \
52 /* If set, can't use UART; jump to save no UART */ \
58 /* Test UART's clock enable bit */ \
60 /* If clear, can't use UART; jump to save no UART */ \
62 /* Passed all tests, load address of UART registers */ \
63 ldr rp, =TEGRA_UART##uart##_BASE ; \
64 /* Jump to save UART address */ \
85 cmp \rv, #2 @ 2 and 3 mean DCC, UART
89 11: lsr \rv, \rp, #15 @ 17:15 are UART ID
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/OK3568_Linux_fs/kernel/arch/arm/
H A DKconfig.debug112 UART definition, as specified below. Attempting to boot the kernel
129 bool "Kernel low-level debugging via asm9260 UART"
133 their output to an UART or USART port on asm9260 based
195 bool "Kernel low-level debugging on BCM2835 PL011 UART"
200 bool "Kernel low-level debugging on BCM2836 PL011 UART"
223 bool "Kernel low-level debugging messages via BCM KONA UART"
234 bool "Kernel low-level debugging on BCM63XX UART"
238 bool "Marvell Berlin SoC Debug UART"
246 bool "Use BRCMSTB UART for low-level debug"
251 UART physical and virtual address is automatically provided
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/OK3568_Linux_fs/kernel/include/uapi/linux/
H A Dserial_core.h31 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
32 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
33 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
34 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
35 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
36 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */
37 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
41 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
42 #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
43 #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
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