1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Synopsys DesignWare ABP UART 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Rob Herring <robh@kernel.org> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunallOf: 13*4882a593Smuzhiyun - $ref: /schemas/serial.yaml# 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun oneOf: 18*4882a593Smuzhiyun - items: 19*4882a593Smuzhiyun - enum: 20*4882a593Smuzhiyun - renesas,r9a06g032-uart 21*4882a593Smuzhiyun - renesas,r9a06g033-uart 22*4882a593Smuzhiyun - const: renesas,rzn1-uart 23*4882a593Smuzhiyun - items: 24*4882a593Smuzhiyun - enum: 25*4882a593Smuzhiyun - rockchip,px30-uart 26*4882a593Smuzhiyun - rockchip,rk3036-uart 27*4882a593Smuzhiyun - rockchip,rk3066-uart 28*4882a593Smuzhiyun - rockchip,rk3188-uart 29*4882a593Smuzhiyun - rockchip,rk3288-uart 30*4882a593Smuzhiyun - rockchip,rk3308-uart 31*4882a593Smuzhiyun - rockchip,rk3328-uart 32*4882a593Smuzhiyun - rockchip,rk3368-uart 33*4882a593Smuzhiyun - rockchip,rk3399-uart 34*4882a593Smuzhiyun - rockchip,rv1108-uart 35*4882a593Smuzhiyun - const: snps,dw-apb-uart 36*4882a593Smuzhiyun - items: 37*4882a593Smuzhiyun - enum: 38*4882a593Smuzhiyun - brcm,bcm11351-dw-apb-uart 39*4882a593Smuzhiyun - brcm,bcm21664-dw-apb-uart 40*4882a593Smuzhiyun - const: snps,dw-apb-uart 41*4882a593Smuzhiyun - const: snps,dw-apb-uart 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun reg: 44*4882a593Smuzhiyun maxItems: 1 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun interrupts: 47*4882a593Smuzhiyun maxItems: 1 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun clock-frequency: true 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun clocks: 52*4882a593Smuzhiyun minItems: 1 53*4882a593Smuzhiyun maxItems: 2 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun clock-names: 56*4882a593Smuzhiyun items: 57*4882a593Smuzhiyun - const: baudclk 58*4882a593Smuzhiyun - const: apb_pclk 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun snps,uart-16550-compatible: 61*4882a593Smuzhiyun description: reflects the value of UART_16550_COMPATIBLE configuration 62*4882a593Smuzhiyun parameter. Define this if your UART does not implement the busy functionality. 63*4882a593Smuzhiyun type: boolean 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun resets: 66*4882a593Smuzhiyun maxItems: 1 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun reg-shift: true 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun reg-io-width: true 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun dcd-override: 73*4882a593Smuzhiyun description: Override the DCD modem status signal. This signal will 74*4882a593Smuzhiyun always be reported as active instead of being obtained from the modem 75*4882a593Smuzhiyun status register. Define this if your serial port does not use this 76*4882a593Smuzhiyun pin. 77*4882a593Smuzhiyun type: boolean 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun dsr-override: 80*4882a593Smuzhiyun description: Override the DTS modem status signal. This signal will 81*4882a593Smuzhiyun always be reported as active instead of being obtained from the modem 82*4882a593Smuzhiyun status register. Define this if your serial port does not use this 83*4882a593Smuzhiyun pin. 84*4882a593Smuzhiyun type: boolean 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun cts-override: 87*4882a593Smuzhiyun description: Override the CTS modem status signal. This signal will 88*4882a593Smuzhiyun always be reported as active instead of being obtained from the modem 89*4882a593Smuzhiyun status register. Define this if your serial port does not use this 90*4882a593Smuzhiyun pin. 91*4882a593Smuzhiyun type: boolean 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun ri-override: 94*4882a593Smuzhiyun description: Override the RI modem status signal. This signal will always 95*4882a593Smuzhiyun be reported as inactive instead of being obtained from the modem status 96*4882a593Smuzhiyun register. Define this if your serial port does not use this pin. 97*4882a593Smuzhiyun type: boolean 98*4882a593Smuzhiyun 99*4882a593Smuzhiyunrequired: 100*4882a593Smuzhiyun - compatible 101*4882a593Smuzhiyun - reg 102*4882a593Smuzhiyun - interrupts 103*4882a593Smuzhiyun 104*4882a593SmuzhiyununevaluatedProperties: false 105*4882a593Smuzhiyun 106*4882a593Smuzhiyunexamples: 107*4882a593Smuzhiyun - | 108*4882a593Smuzhiyun serial@80230000 { 109*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 110*4882a593Smuzhiyun reg = <0x80230000 0x100>; 111*4882a593Smuzhiyun clock-frequency = <3686400>; 112*4882a593Smuzhiyun interrupts = <10>; 113*4882a593Smuzhiyun reg-shift = <2>; 114*4882a593Smuzhiyun reg-io-width = <4>; 115*4882a593Smuzhiyun dcd-override; 116*4882a593Smuzhiyun dsr-override; 117*4882a593Smuzhiyun cts-override; 118*4882a593Smuzhiyun ri-override; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun - | 122*4882a593Smuzhiyun // Example with one clock: 123*4882a593Smuzhiyun serial@80230000 { 124*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 125*4882a593Smuzhiyun reg = <0x80230000 0x100>; 126*4882a593Smuzhiyun clocks = <&baudclk>; 127*4882a593Smuzhiyun interrupts = <10>; 128*4882a593Smuzhiyun reg-shift = <2>; 129*4882a593Smuzhiyun reg-io-width = <4>; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun - | 133*4882a593Smuzhiyun // Example with two clocks: 134*4882a593Smuzhiyun serial@80230000 { 135*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 136*4882a593Smuzhiyun reg = <0x80230000 0x100>; 137*4882a593Smuzhiyun clocks = <&baudclk>, <&apb_pclk>; 138*4882a593Smuzhiyun clock-names = "baudclk", "apb_pclk"; 139*4882a593Smuzhiyun interrupts = <10>; 140*4882a593Smuzhiyun reg-shift = <2>; 141*4882a593Smuzhiyun reg-io-width = <4>; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun... 144