1*4882a593Smuzhiyun* CSR SiRFprimaII/atlasVI Universal Synchronous Asynchronous Receiver/Transmitter * 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart", 5*4882a593Smuzhiyun "sirf,atlas7-uart" or "sirf,atlas7-usp-uart". 6*4882a593Smuzhiyun- reg : Offset and length of the register set for the device 7*4882a593Smuzhiyun- interrupts : Should contain uart interrupt 8*4882a593Smuzhiyun- fifosize : Should define hardware rx/tx fifo size 9*4882a593Smuzhiyun- clocks : Should contain uart clock number 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunOptional properties: 12*4882a593Smuzhiyun- uart-has-rtscts: we have hardware flow controller pins in hardware 13*4882a593Smuzhiyun- rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true 14*4882a593Smuzhiyun- cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunuart0: uart@b0050000 { 19*4882a593Smuzhiyun cell-index = <0>; 20*4882a593Smuzhiyun compatible = "sirf,prima2-uart"; 21*4882a593Smuzhiyun reg = <0xb0050000 0x1000>; 22*4882a593Smuzhiyun interrupts = <17>; 23*4882a593Smuzhiyun fifosize = <128>; 24*4882a593Smuzhiyun clocks = <&clks 13>; 25*4882a593Smuzhiyun}; 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunOn the board-specific dts, we can put rts-gpios and cts-gpios like 28*4882a593Smuzhiyun 29*4882a593Smuzhiyunusp@b0090000 { 30*4882a593Smuzhiyun compatible = "sirf,prima2-usp-uart"; 31*4882a593Smuzhiyun uart-has-rtscts; 32*4882a593Smuzhiyun rts-gpios = <&gpio 15 0>; 33*4882a593Smuzhiyun cts-gpios = <&gpio 46 0>; 34*4882a593Smuzhiyun}; 35