1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * timbuart.c timberdale FPGA UART driver
4*4882a593Smuzhiyun * Copyright (c) 2009 Intel Corporation
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun /* Supports:
8*4882a593Smuzhiyun * Timberdale FPGA UART
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/pci.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <linux/serial_core.h>
14*4882a593Smuzhiyun #include <linux/tty.h>
15*4882a593Smuzhiyun #include <linux/tty_flip.h>
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/platform_device.h>
18*4882a593Smuzhiyun #include <linux/ioport.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun #include <linux/module.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include "timbuart.h"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct timbuart_port {
25*4882a593Smuzhiyun struct uart_port port;
26*4882a593Smuzhiyun struct tasklet_struct tasklet;
27*4882a593Smuzhiyun int usedma;
28*4882a593Smuzhiyun u32 last_ier;
29*4882a593Smuzhiyun struct platform_device *dev;
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static int baudrates[] = {9600, 19200, 38400, 57600, 115200, 230400, 460800,
33*4882a593Smuzhiyun 921600, 1843200, 3250000};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static void timbuart_mctrl_check(struct uart_port *port, u32 isr, u32 *ier);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun static irqreturn_t timbuart_handleinterrupt(int irq, void *devid);
38*4882a593Smuzhiyun
timbuart_stop_rx(struct uart_port * port)39*4882a593Smuzhiyun static void timbuart_stop_rx(struct uart_port *port)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun /* spin lock held by upper layer, disable all RX interrupts */
42*4882a593Smuzhiyun u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS;
43*4882a593Smuzhiyun iowrite32(ier, port->membase + TIMBUART_IER);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
timbuart_stop_tx(struct uart_port * port)46*4882a593Smuzhiyun static void timbuart_stop_tx(struct uart_port *port)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun /* spinlock held by upper layer, disable TX interrupt */
49*4882a593Smuzhiyun u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE;
50*4882a593Smuzhiyun iowrite32(ier, port->membase + TIMBUART_IER);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
timbuart_start_tx(struct uart_port * port)53*4882a593Smuzhiyun static void timbuart_start_tx(struct uart_port *port)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct timbuart_port *uart =
56*4882a593Smuzhiyun container_of(port, struct timbuart_port, port);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* do not transfer anything here -> fire off the tasklet */
59*4882a593Smuzhiyun tasklet_schedule(&uart->tasklet);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
timbuart_tx_empty(struct uart_port * port)62*4882a593Smuzhiyun static unsigned int timbuart_tx_empty(struct uart_port *port)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun u32 isr = ioread32(port->membase + TIMBUART_ISR);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun return (isr & TXBE) ? TIOCSER_TEMT : 0;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
timbuart_flush_buffer(struct uart_port * port)69*4882a593Smuzhiyun static void timbuart_flush_buffer(struct uart_port *port)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun if (!timbuart_tx_empty(port)) {
72*4882a593Smuzhiyun u8 ctl = ioread8(port->membase + TIMBUART_CTRL) |
73*4882a593Smuzhiyun TIMBUART_CTRL_FLSHTX;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun iowrite8(ctl, port->membase + TIMBUART_CTRL);
76*4882a593Smuzhiyun iowrite32(TXBF, port->membase + TIMBUART_ISR);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
timbuart_rx_chars(struct uart_port * port)80*4882a593Smuzhiyun static void timbuart_rx_chars(struct uart_port *port)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun struct tty_port *tport = &port->state->port;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun while (ioread32(port->membase + TIMBUART_ISR) & RXDP) {
85*4882a593Smuzhiyun u8 ch = ioread8(port->membase + TIMBUART_RXFIFO);
86*4882a593Smuzhiyun port->icount.rx++;
87*4882a593Smuzhiyun tty_insert_flip_char(tport, ch, TTY_NORMAL);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun spin_unlock(&port->lock);
91*4882a593Smuzhiyun tty_flip_buffer_push(tport);
92*4882a593Smuzhiyun spin_lock(&port->lock);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun dev_dbg(port->dev, "%s - total read %d bytes\n",
95*4882a593Smuzhiyun __func__, port->icount.rx);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
timbuart_tx_chars(struct uart_port * port)98*4882a593Smuzhiyun static void timbuart_tx_chars(struct uart_port *port)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun struct circ_buf *xmit = &port->state->xmit;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun while (!(ioread32(port->membase + TIMBUART_ISR) & TXBF) &&
103*4882a593Smuzhiyun !uart_circ_empty(xmit)) {
104*4882a593Smuzhiyun iowrite8(xmit->buf[xmit->tail],
105*4882a593Smuzhiyun port->membase + TIMBUART_TXFIFO);
106*4882a593Smuzhiyun xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
107*4882a593Smuzhiyun port->icount.tx++;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun dev_dbg(port->dev,
111*4882a593Smuzhiyun "%s - total written %d bytes, CTL: %x, RTS: %x, baud: %x\n",
112*4882a593Smuzhiyun __func__,
113*4882a593Smuzhiyun port->icount.tx,
114*4882a593Smuzhiyun ioread8(port->membase + TIMBUART_CTRL),
115*4882a593Smuzhiyun port->mctrl & TIOCM_RTS,
116*4882a593Smuzhiyun ioread8(port->membase + TIMBUART_BAUDRATE));
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
timbuart_handle_tx_port(struct uart_port * port,u32 isr,u32 * ier)119*4882a593Smuzhiyun static void timbuart_handle_tx_port(struct uart_port *port, u32 isr, u32 *ier)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun struct timbuart_port *uart =
122*4882a593Smuzhiyun container_of(port, struct timbuart_port, port);
123*4882a593Smuzhiyun struct circ_buf *xmit = &port->state->xmit;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun if (uart_circ_empty(xmit) || uart_tx_stopped(port))
126*4882a593Smuzhiyun return;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun if (port->x_char)
129*4882a593Smuzhiyun return;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun if (isr & TXFLAGS) {
132*4882a593Smuzhiyun timbuart_tx_chars(port);
133*4882a593Smuzhiyun /* clear all TX interrupts */
134*4882a593Smuzhiyun iowrite32(TXFLAGS, port->membase + TIMBUART_ISR);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
137*4882a593Smuzhiyun uart_write_wakeup(port);
138*4882a593Smuzhiyun } else
139*4882a593Smuzhiyun /* Re-enable any tx interrupt */
140*4882a593Smuzhiyun *ier |= uart->last_ier & TXFLAGS;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /* enable interrupts if there are chars in the transmit buffer,
143*4882a593Smuzhiyun * Or if we delivered some bytes and want the almost empty interrupt
144*4882a593Smuzhiyun * we wake up the upper layer later when we got the interrupt
145*4882a593Smuzhiyun * to give it some time to go out...
146*4882a593Smuzhiyun */
147*4882a593Smuzhiyun if (!uart_circ_empty(xmit))
148*4882a593Smuzhiyun *ier |= TXBAE;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun dev_dbg(port->dev, "%s - leaving\n", __func__);
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
timbuart_handle_rx_port(struct uart_port * port,u32 isr,u32 * ier)153*4882a593Smuzhiyun static void timbuart_handle_rx_port(struct uart_port *port, u32 isr, u32 *ier)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun if (isr & RXFLAGS) {
156*4882a593Smuzhiyun /* Some RX status is set */
157*4882a593Smuzhiyun if (isr & RXBF) {
158*4882a593Smuzhiyun u8 ctl = ioread8(port->membase + TIMBUART_CTRL) |
159*4882a593Smuzhiyun TIMBUART_CTRL_FLSHRX;
160*4882a593Smuzhiyun iowrite8(ctl, port->membase + TIMBUART_CTRL);
161*4882a593Smuzhiyun port->icount.overrun++;
162*4882a593Smuzhiyun } else if (isr & (RXDP))
163*4882a593Smuzhiyun timbuart_rx_chars(port);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /* ack all RX interrupts */
166*4882a593Smuzhiyun iowrite32(RXFLAGS, port->membase + TIMBUART_ISR);
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun /* always have the RX interrupts enabled */
170*4882a593Smuzhiyun *ier |= RXBAF | RXBF | RXTT;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun dev_dbg(port->dev, "%s - leaving\n", __func__);
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
timbuart_tasklet(struct tasklet_struct * t)175*4882a593Smuzhiyun static void timbuart_tasklet(struct tasklet_struct *t)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun struct timbuart_port *uart = from_tasklet(uart, t, tasklet);
178*4882a593Smuzhiyun u32 isr, ier = 0;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun spin_lock(&uart->port.lock);
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun isr = ioread32(uart->port.membase + TIMBUART_ISR);
183*4882a593Smuzhiyun dev_dbg(uart->port.dev, "%s ISR: %x\n", __func__, isr);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun if (!uart->usedma)
186*4882a593Smuzhiyun timbuart_handle_tx_port(&uart->port, isr, &ier);
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun timbuart_mctrl_check(&uart->port, isr, &ier);
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun if (!uart->usedma)
191*4882a593Smuzhiyun timbuart_handle_rx_port(&uart->port, isr, &ier);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun iowrite32(ier, uart->port.membase + TIMBUART_IER);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun spin_unlock(&uart->port.lock);
196*4882a593Smuzhiyun dev_dbg(uart->port.dev, "%s leaving\n", __func__);
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
timbuart_get_mctrl(struct uart_port * port)199*4882a593Smuzhiyun static unsigned int timbuart_get_mctrl(struct uart_port *port)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun u8 cts = ioread8(port->membase + TIMBUART_CTRL);
202*4882a593Smuzhiyun dev_dbg(port->dev, "%s - cts %x\n", __func__, cts);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun if (cts & TIMBUART_CTRL_CTS)
205*4882a593Smuzhiyun return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
206*4882a593Smuzhiyun else
207*4882a593Smuzhiyun return TIOCM_DSR | TIOCM_CAR;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
timbuart_set_mctrl(struct uart_port * port,unsigned int mctrl)210*4882a593Smuzhiyun static void timbuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun dev_dbg(port->dev, "%s - %x\n", __func__, mctrl);
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun if (mctrl & TIOCM_RTS)
215*4882a593Smuzhiyun iowrite8(TIMBUART_CTRL_RTS, port->membase + TIMBUART_CTRL);
216*4882a593Smuzhiyun else
217*4882a593Smuzhiyun iowrite8(0, port->membase + TIMBUART_CTRL);
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
timbuart_mctrl_check(struct uart_port * port,u32 isr,u32 * ier)220*4882a593Smuzhiyun static void timbuart_mctrl_check(struct uart_port *port, u32 isr, u32 *ier)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun unsigned int cts;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun if (isr & CTS_DELTA) {
225*4882a593Smuzhiyun /* ack */
226*4882a593Smuzhiyun iowrite32(CTS_DELTA, port->membase + TIMBUART_ISR);
227*4882a593Smuzhiyun cts = timbuart_get_mctrl(port);
228*4882a593Smuzhiyun uart_handle_cts_change(port, cts & TIOCM_CTS);
229*4882a593Smuzhiyun wake_up_interruptible(&port->state->port.delta_msr_wait);
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun *ier |= CTS_DELTA;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
timbuart_break_ctl(struct uart_port * port,int ctl)235*4882a593Smuzhiyun static void timbuart_break_ctl(struct uart_port *port, int ctl)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun /* N/A */
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun
timbuart_startup(struct uart_port * port)240*4882a593Smuzhiyun static int timbuart_startup(struct uart_port *port)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun struct timbuart_port *uart =
243*4882a593Smuzhiyun container_of(port, struct timbuart_port, port);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun dev_dbg(port->dev, "%s\n", __func__);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun iowrite8(TIMBUART_CTRL_FLSHRX, port->membase + TIMBUART_CTRL);
248*4882a593Smuzhiyun iowrite32(0x1ff, port->membase + TIMBUART_ISR);
249*4882a593Smuzhiyun /* Enable all but TX interrupts */
250*4882a593Smuzhiyun iowrite32(RXBAF | RXBF | RXTT | CTS_DELTA,
251*4882a593Smuzhiyun port->membase + TIMBUART_IER);
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun return request_irq(port->irq, timbuart_handleinterrupt, IRQF_SHARED,
254*4882a593Smuzhiyun "timb-uart", uart);
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
timbuart_shutdown(struct uart_port * port)257*4882a593Smuzhiyun static void timbuart_shutdown(struct uart_port *port)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun struct timbuart_port *uart =
260*4882a593Smuzhiyun container_of(port, struct timbuart_port, port);
261*4882a593Smuzhiyun dev_dbg(port->dev, "%s\n", __func__);
262*4882a593Smuzhiyun free_irq(port->irq, uart);
263*4882a593Smuzhiyun iowrite32(0, port->membase + TIMBUART_IER);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun timbuart_flush_buffer(port);
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
get_bindex(int baud)268*4882a593Smuzhiyun static int get_bindex(int baud)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun int i;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(baudrates); i++)
273*4882a593Smuzhiyun if (baud <= baudrates[i])
274*4882a593Smuzhiyun return i;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun return -1;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
timbuart_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)279*4882a593Smuzhiyun static void timbuart_set_termios(struct uart_port *port,
280*4882a593Smuzhiyun struct ktermios *termios,
281*4882a593Smuzhiyun struct ktermios *old)
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun unsigned int baud;
284*4882a593Smuzhiyun short bindex;
285*4882a593Smuzhiyun unsigned long flags;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
288*4882a593Smuzhiyun bindex = get_bindex(baud);
289*4882a593Smuzhiyun dev_dbg(port->dev, "%s - bindex %d\n", __func__, bindex);
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun if (bindex < 0)
292*4882a593Smuzhiyun bindex = 0;
293*4882a593Smuzhiyun baud = baudrates[bindex];
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun /* The serial layer calls into this once with old = NULL when setting
296*4882a593Smuzhiyun up initially */
297*4882a593Smuzhiyun if (old)
298*4882a593Smuzhiyun tty_termios_copy_hw(termios, old);
299*4882a593Smuzhiyun tty_termios_encode_baud_rate(termios, baud, baud);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun spin_lock_irqsave(&port->lock, flags);
302*4882a593Smuzhiyun iowrite8((u8)bindex, port->membase + TIMBUART_BAUDRATE);
303*4882a593Smuzhiyun uart_update_timeout(port, termios->c_cflag, baud);
304*4882a593Smuzhiyun spin_unlock_irqrestore(&port->lock, flags);
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun
timbuart_type(struct uart_port * port)307*4882a593Smuzhiyun static const char *timbuart_type(struct uart_port *port)
308*4882a593Smuzhiyun {
309*4882a593Smuzhiyun return port->type == PORT_UNKNOWN ? "timbuart" : NULL;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun /* We do not request/release mappings of the registers here,
313*4882a593Smuzhiyun * currently it's done in the proble function.
314*4882a593Smuzhiyun */
timbuart_release_port(struct uart_port * port)315*4882a593Smuzhiyun static void timbuart_release_port(struct uart_port *port)
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun struct platform_device *pdev = to_platform_device(port->dev);
318*4882a593Smuzhiyun int size =
319*4882a593Smuzhiyun resource_size(platform_get_resource(pdev, IORESOURCE_MEM, 0));
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun if (port->flags & UPF_IOREMAP) {
322*4882a593Smuzhiyun iounmap(port->membase);
323*4882a593Smuzhiyun port->membase = NULL;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun release_mem_region(port->mapbase, size);
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
timbuart_request_port(struct uart_port * port)329*4882a593Smuzhiyun static int timbuart_request_port(struct uart_port *port)
330*4882a593Smuzhiyun {
331*4882a593Smuzhiyun struct platform_device *pdev = to_platform_device(port->dev);
332*4882a593Smuzhiyun int size =
333*4882a593Smuzhiyun resource_size(platform_get_resource(pdev, IORESOURCE_MEM, 0));
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun if (!request_mem_region(port->mapbase, size, "timb-uart"))
336*4882a593Smuzhiyun return -EBUSY;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun if (port->flags & UPF_IOREMAP) {
339*4882a593Smuzhiyun port->membase = ioremap(port->mapbase, size);
340*4882a593Smuzhiyun if (port->membase == NULL) {
341*4882a593Smuzhiyun release_mem_region(port->mapbase, size);
342*4882a593Smuzhiyun return -ENOMEM;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun return 0;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
timbuart_handleinterrupt(int irq,void * devid)349*4882a593Smuzhiyun static irqreturn_t timbuart_handleinterrupt(int irq, void *devid)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun struct timbuart_port *uart = (struct timbuart_port *)devid;
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun if (ioread8(uart->port.membase + TIMBUART_IPR)) {
354*4882a593Smuzhiyun uart->last_ier = ioread32(uart->port.membase + TIMBUART_IER);
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun /* disable interrupts, the tasklet enables them again */
357*4882a593Smuzhiyun iowrite32(0, uart->port.membase + TIMBUART_IER);
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun /* fire off bottom half */
360*4882a593Smuzhiyun tasklet_schedule(&uart->tasklet);
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun return IRQ_HANDLED;
363*4882a593Smuzhiyun } else
364*4882a593Smuzhiyun return IRQ_NONE;
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun /*
368*4882a593Smuzhiyun * Configure/autoconfigure the port.
369*4882a593Smuzhiyun */
timbuart_config_port(struct uart_port * port,int flags)370*4882a593Smuzhiyun static void timbuart_config_port(struct uart_port *port, int flags)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun if (flags & UART_CONFIG_TYPE) {
373*4882a593Smuzhiyun port->type = PORT_TIMBUART;
374*4882a593Smuzhiyun timbuart_request_port(port);
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun
timbuart_verify_port(struct uart_port * port,struct serial_struct * ser)378*4882a593Smuzhiyun static int timbuart_verify_port(struct uart_port *port,
379*4882a593Smuzhiyun struct serial_struct *ser)
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun /* we don't want the core code to modify any port params */
382*4882a593Smuzhiyun return -EINVAL;
383*4882a593Smuzhiyun }
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun static const struct uart_ops timbuart_ops = {
386*4882a593Smuzhiyun .tx_empty = timbuart_tx_empty,
387*4882a593Smuzhiyun .set_mctrl = timbuart_set_mctrl,
388*4882a593Smuzhiyun .get_mctrl = timbuart_get_mctrl,
389*4882a593Smuzhiyun .stop_tx = timbuart_stop_tx,
390*4882a593Smuzhiyun .start_tx = timbuart_start_tx,
391*4882a593Smuzhiyun .flush_buffer = timbuart_flush_buffer,
392*4882a593Smuzhiyun .stop_rx = timbuart_stop_rx,
393*4882a593Smuzhiyun .break_ctl = timbuart_break_ctl,
394*4882a593Smuzhiyun .startup = timbuart_startup,
395*4882a593Smuzhiyun .shutdown = timbuart_shutdown,
396*4882a593Smuzhiyun .set_termios = timbuart_set_termios,
397*4882a593Smuzhiyun .type = timbuart_type,
398*4882a593Smuzhiyun .release_port = timbuart_release_port,
399*4882a593Smuzhiyun .request_port = timbuart_request_port,
400*4882a593Smuzhiyun .config_port = timbuart_config_port,
401*4882a593Smuzhiyun .verify_port = timbuart_verify_port
402*4882a593Smuzhiyun };
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun static struct uart_driver timbuart_driver = {
405*4882a593Smuzhiyun .owner = THIS_MODULE,
406*4882a593Smuzhiyun .driver_name = "timberdale_uart",
407*4882a593Smuzhiyun .dev_name = "ttyTU",
408*4882a593Smuzhiyun .major = TIMBUART_MAJOR,
409*4882a593Smuzhiyun .minor = TIMBUART_MINOR,
410*4882a593Smuzhiyun .nr = 1
411*4882a593Smuzhiyun };
412*4882a593Smuzhiyun
timbuart_probe(struct platform_device * dev)413*4882a593Smuzhiyun static int timbuart_probe(struct platform_device *dev)
414*4882a593Smuzhiyun {
415*4882a593Smuzhiyun int err, irq;
416*4882a593Smuzhiyun struct timbuart_port *uart;
417*4882a593Smuzhiyun struct resource *iomem;
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun dev_dbg(&dev->dev, "%s\n", __func__);
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun uart = kzalloc(sizeof(*uart), GFP_KERNEL);
422*4882a593Smuzhiyun if (!uart) {
423*4882a593Smuzhiyun err = -EINVAL;
424*4882a593Smuzhiyun goto err_mem;
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun uart->usedma = 0;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun uart->port.uartclk = 3250000 * 16;
430*4882a593Smuzhiyun uart->port.fifosize = TIMBUART_FIFO_SIZE;
431*4882a593Smuzhiyun uart->port.regshift = 2;
432*4882a593Smuzhiyun uart->port.iotype = UPIO_MEM;
433*4882a593Smuzhiyun uart->port.ops = &timbuart_ops;
434*4882a593Smuzhiyun uart->port.irq = 0;
435*4882a593Smuzhiyun uart->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
436*4882a593Smuzhiyun uart->port.line = 0;
437*4882a593Smuzhiyun uart->port.dev = &dev->dev;
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
440*4882a593Smuzhiyun if (!iomem) {
441*4882a593Smuzhiyun err = -ENOMEM;
442*4882a593Smuzhiyun goto err_register;
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun uart->port.mapbase = iomem->start;
445*4882a593Smuzhiyun uart->port.membase = NULL;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun irq = platform_get_irq(dev, 0);
448*4882a593Smuzhiyun if (irq < 0) {
449*4882a593Smuzhiyun err = -EINVAL;
450*4882a593Smuzhiyun goto err_register;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun uart->port.irq = irq;
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun tasklet_setup(&uart->tasklet, timbuart_tasklet);
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun err = uart_register_driver(&timbuart_driver);
457*4882a593Smuzhiyun if (err)
458*4882a593Smuzhiyun goto err_register;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun err = uart_add_one_port(&timbuart_driver, &uart->port);
461*4882a593Smuzhiyun if (err)
462*4882a593Smuzhiyun goto err_add_port;
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun platform_set_drvdata(dev, uart);
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun return 0;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun err_add_port:
469*4882a593Smuzhiyun uart_unregister_driver(&timbuart_driver);
470*4882a593Smuzhiyun err_register:
471*4882a593Smuzhiyun kfree(uart);
472*4882a593Smuzhiyun err_mem:
473*4882a593Smuzhiyun printk(KERN_ERR "timberdale: Failed to register Timberdale UART: %d\n",
474*4882a593Smuzhiyun err);
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun return err;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun
timbuart_remove(struct platform_device * dev)479*4882a593Smuzhiyun static int timbuart_remove(struct platform_device *dev)
480*4882a593Smuzhiyun {
481*4882a593Smuzhiyun struct timbuart_port *uart = platform_get_drvdata(dev);
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun tasklet_kill(&uart->tasklet);
484*4882a593Smuzhiyun uart_remove_one_port(&timbuart_driver, &uart->port);
485*4882a593Smuzhiyun uart_unregister_driver(&timbuart_driver);
486*4882a593Smuzhiyun kfree(uart);
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun return 0;
489*4882a593Smuzhiyun }
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun static struct platform_driver timbuart_platform_driver = {
492*4882a593Smuzhiyun .driver = {
493*4882a593Smuzhiyun .name = "timb-uart",
494*4882a593Smuzhiyun },
495*4882a593Smuzhiyun .probe = timbuart_probe,
496*4882a593Smuzhiyun .remove = timbuart_remove,
497*4882a593Smuzhiyun };
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun module_platform_driver(timbuart_platform_driver);
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun MODULE_DESCRIPTION("Timberdale UART driver");
502*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
503*4882a593Smuzhiyun MODULE_ALIAS("platform:timb-uart");
504*4882a593Smuzhiyun
505