1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Serial Port driver for Tegra devices
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/acpi.h>
9*4882a593Smuzhiyun #include <linux/clk.h>
10*4882a593Smuzhiyun #include <linux/console.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/reset.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "8250.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun struct tegra_uart {
20*4882a593Smuzhiyun struct clk *clk;
21*4882a593Smuzhiyun struct reset_control *rst;
22*4882a593Smuzhiyun int line;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
tegra_uart_handle_break(struct uart_port * p)25*4882a593Smuzhiyun static void tegra_uart_handle_break(struct uart_port *p)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun unsigned int status, tmout = 10000;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun do {
30*4882a593Smuzhiyun status = p->serial_in(p, UART_LSR);
31*4882a593Smuzhiyun if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
32*4882a593Smuzhiyun status = p->serial_in(p, UART_RX);
33*4882a593Smuzhiyun else
34*4882a593Smuzhiyun break;
35*4882a593Smuzhiyun if (--tmout == 0)
36*4882a593Smuzhiyun break;
37*4882a593Smuzhiyun udelay(1);
38*4882a593Smuzhiyun } while (1);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
tegra_uart_probe(struct platform_device * pdev)41*4882a593Smuzhiyun static int tegra_uart_probe(struct platform_device *pdev)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun struct uart_8250_port port8250;
44*4882a593Smuzhiyun struct tegra_uart *uart;
45*4882a593Smuzhiyun struct uart_port *port;
46*4882a593Smuzhiyun struct resource *res;
47*4882a593Smuzhiyun int ret;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL);
50*4882a593Smuzhiyun if (!uart)
51*4882a593Smuzhiyun return -ENOMEM;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun memset(&port8250, 0, sizeof(port8250));
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun port = &port8250.port;
56*4882a593Smuzhiyun spin_lock_init(&port->lock);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT |
59*4882a593Smuzhiyun UPF_FIXED_TYPE;
60*4882a593Smuzhiyun port->iotype = UPIO_MEM32;
61*4882a593Smuzhiyun port->regshift = 2;
62*4882a593Smuzhiyun port->type = PORT_TEGRA;
63*4882a593Smuzhiyun port->irqflags |= IRQF_SHARED;
64*4882a593Smuzhiyun port->dev = &pdev->dev;
65*4882a593Smuzhiyun port->handle_break = tegra_uart_handle_break;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun ret = of_alias_get_id(pdev->dev.of_node, "serial");
68*4882a593Smuzhiyun if (ret >= 0)
69*4882a593Smuzhiyun port->line = ret;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun ret = platform_get_irq(pdev, 0);
72*4882a593Smuzhiyun if (ret < 0)
73*4882a593Smuzhiyun return ret;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun port->irq = ret;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
78*4882a593Smuzhiyun if (!res)
79*4882a593Smuzhiyun return -ENODEV;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun port->membase = devm_ioremap(&pdev->dev, res->start,
82*4882a593Smuzhiyun resource_size(res));
83*4882a593Smuzhiyun if (!port->membase)
84*4882a593Smuzhiyun return -ENOMEM;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun port->mapbase = res->start;
87*4882a593Smuzhiyun port->mapsize = resource_size(res);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun uart->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
90*4882a593Smuzhiyun if (IS_ERR(uart->rst))
91*4882a593Smuzhiyun return PTR_ERR(uart->rst);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun if (device_property_read_u32(&pdev->dev, "clock-frequency",
94*4882a593Smuzhiyun &port->uartclk)) {
95*4882a593Smuzhiyun uart->clk = devm_clk_get(&pdev->dev, NULL);
96*4882a593Smuzhiyun if (IS_ERR(uart->clk)) {
97*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get clock!\n");
98*4882a593Smuzhiyun return -ENODEV;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun ret = clk_prepare_enable(uart->clk);
102*4882a593Smuzhiyun if (ret < 0)
103*4882a593Smuzhiyun return ret;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun port->uartclk = clk_get_rate(uart->clk);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun ret = reset_control_deassert(uart->rst);
109*4882a593Smuzhiyun if (ret)
110*4882a593Smuzhiyun goto err_clkdisable;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun ret = serial8250_register_8250_port(&port8250);
113*4882a593Smuzhiyun if (ret < 0)
114*4882a593Smuzhiyun goto err_clkdisable;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun platform_set_drvdata(pdev, uart);
117*4882a593Smuzhiyun uart->line = ret;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun return 0;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun err_clkdisable:
122*4882a593Smuzhiyun clk_disable_unprepare(uart->clk);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun return ret;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
tegra_uart_remove(struct platform_device * pdev)127*4882a593Smuzhiyun static int tegra_uart_remove(struct platform_device *pdev)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun struct tegra_uart *uart = platform_get_drvdata(pdev);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun serial8250_unregister_port(uart->line);
132*4882a593Smuzhiyun reset_control_assert(uart->rst);
133*4882a593Smuzhiyun clk_disable_unprepare(uart->clk);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun return 0;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
tegra_uart_suspend(struct device * dev)139*4882a593Smuzhiyun static int tegra_uart_suspend(struct device *dev)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun struct tegra_uart *uart = dev_get_drvdata(dev);
142*4882a593Smuzhiyun struct uart_8250_port *port8250 = serial8250_get_port(uart->line);
143*4882a593Smuzhiyun struct uart_port *port = &port8250->port;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun serial8250_suspend_port(uart->line);
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun if (!uart_console(port) || console_suspend_enabled)
148*4882a593Smuzhiyun clk_disable_unprepare(uart->clk);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun return 0;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
tegra_uart_resume(struct device * dev)153*4882a593Smuzhiyun static int tegra_uart_resume(struct device *dev)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun struct tegra_uart *uart = dev_get_drvdata(dev);
156*4882a593Smuzhiyun struct uart_8250_port *port8250 = serial8250_get_port(uart->line);
157*4882a593Smuzhiyun struct uart_port *port = &port8250->port;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun if (!uart_console(port) || console_suspend_enabled)
160*4882a593Smuzhiyun clk_prepare_enable(uart->clk);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun serial8250_resume_port(uart->line);
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun return 0;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun #endif
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(tegra_uart_pm_ops, tegra_uart_suspend,
169*4882a593Smuzhiyun tegra_uart_resume);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun static const struct of_device_id tegra_uart_of_match[] = {
172*4882a593Smuzhiyun { .compatible = "nvidia,tegra20-uart", },
173*4882a593Smuzhiyun { },
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun static const struct acpi_device_id tegra_uart_acpi_match[] = {
178*4882a593Smuzhiyun { "NVDA0100", 0 },
179*4882a593Smuzhiyun { },
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, tegra_uart_acpi_match);
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun static struct platform_driver tegra_uart_driver = {
184*4882a593Smuzhiyun .driver = {
185*4882a593Smuzhiyun .name = "tegra-uart",
186*4882a593Smuzhiyun .pm = &tegra_uart_pm_ops,
187*4882a593Smuzhiyun .of_match_table = tegra_uart_of_match,
188*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(tegra_uart_acpi_match),
189*4882a593Smuzhiyun },
190*4882a593Smuzhiyun .probe = tegra_uart_probe,
191*4882a593Smuzhiyun .remove = tegra_uart_remove,
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun module_platform_driver(tegra_uart_driver);
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun MODULE_AUTHOR("Jeff Brasen <jbrasen@nvidia.com>");
197*4882a593Smuzhiyun MODULE_DESCRIPTION("NVIDIA Tegra 8250 Driver");
198*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
199