1*4882a593Smuzhiyun* MediaTek Universal Asynchronous Receiver/Transmitter (UART) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible should contain: 5*4882a593Smuzhiyun * "mediatek,mt2701-uart" for MT2701 compatible UARTS 6*4882a593Smuzhiyun * "mediatek,mt2712-uart" for MT2712 compatible UARTS 7*4882a593Smuzhiyun * "mediatek,mt6580-uart" for MT6580 compatible UARTS 8*4882a593Smuzhiyun * "mediatek,mt6582-uart" for MT6582 compatible UARTS 9*4882a593Smuzhiyun * "mediatek,mt6589-uart" for MT6589 compatible UARTS 10*4882a593Smuzhiyun * "mediatek,mt6755-uart" for MT6755 compatible UARTS 11*4882a593Smuzhiyun * "mediatek,mt6765-uart" for MT6765 compatible UARTS 12*4882a593Smuzhiyun * "mediatek,mt6779-uart" for MT6779 compatible UARTS 13*4882a593Smuzhiyun * "mediatek,mt6795-uart" for MT6795 compatible UARTS 14*4882a593Smuzhiyun * "mediatek,mt6797-uart" for MT6797 compatible UARTS 15*4882a593Smuzhiyun * "mediatek,mt7622-uart" for MT7622 compatible UARTS 16*4882a593Smuzhiyun * "mediatek,mt7623-uart" for MT7623 compatible UARTS 17*4882a593Smuzhiyun * "mediatek,mt7629-uart" for MT7629 compatible UARTS 18*4882a593Smuzhiyun * "mediatek,mt8127-uart" for MT8127 compatible UARTS 19*4882a593Smuzhiyun * "mediatek,mt8135-uart" for MT8135 compatible UARTS 20*4882a593Smuzhiyun * "mediatek,mt8173-uart" for MT8173 compatible UARTS 21*4882a593Smuzhiyun * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS 22*4882a593Smuzhiyun * "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible UARTS 23*4882a593Smuzhiyun * "mediatek,mt8516-uart" for MT8516 compatible UARTS 24*4882a593Smuzhiyun * "mediatek,mt6577-uart" for MT6577 and all of the above 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun- reg: The base address of the UART register bank. 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun- interrupts: 29*4882a593Smuzhiyun index 0: an interrupt specifier for the UART controller itself 30*4882a593Smuzhiyun index 1: optional, an interrupt specifier with edge sensitivity on Rx pin to 31*4882a593Smuzhiyun support Rx in-band wake up. If one would like to use this feature, 32*4882a593Smuzhiyun one must create an addtional pinctrl to reconfigure Rx pin to normal 33*4882a593Smuzhiyun GPIO before suspend. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun- clocks : Must contain an entry for each entry in clock-names. 36*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 37*4882a593Smuzhiyun- clock-names: 38*4882a593Smuzhiyun - "baud": The clock the baudrate is derived from 39*4882a593Smuzhiyun - "bus": The bus clock for register accesses (optional) 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunFor compatibility with older device trees an unnamed clock is used for the 42*4882a593Smuzhiyunbaud clock if the baudclk does not exist. Do not use this for new designs. 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunExample: 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun uart0: serial@11006000 { 47*4882a593Smuzhiyun compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart"; 48*4882a593Smuzhiyun reg = <0x11006000 0x400>; 49*4882a593Smuzhiyun interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, 50*4882a593Smuzhiyun <GIC_SPI 52 IRQ_TYPE_EDGE_FALLING>; 51*4882a593Smuzhiyun clocks = <&uart_clk>, <&bus_clk>; 52*4882a593Smuzhiyun clock-names = "baud", "bus"; 53*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 54*4882a593Smuzhiyun pinctrl-0 = <&uart_pin>; 55*4882a593Smuzhiyun pinctrl-1 = <&uart_pin_sleep>; 56*4882a593Smuzhiyun }; 57