| /OK3568_Linux_fs/u-boot/arch/arm/mach-uniphier/clk/ |
| H A D | pll-ld4.c | 18 u32 tmp, clk_mode_upll, clk_mode_axosel; in upll_init() local
20 tmp = readl(SG_PINMON0); in upll_init()
21 clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; in upll_init()
22 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; in upll_init()
25 tmp = readl(SC_UPLLCTRL); in upll_init()
26 tmp &= ~0x18000000; in upll_init()
27 writel(tmp, SC_UPLLCTRL); in upll_init()
33 tmp &= ~0x07ffffff; in upll_init()
34 tmp |= 0x0228f5c0; in upll_init()
37 tmp &= ~0x07ffffff; in upll_init()
[all …]
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| H A D | pll-pro4.c | 18 u32 tmp, clk_mode_axosel; in vpll_init() local
21 tmp = readl(SG_PINMON0); in vpll_init()
22 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; in vpll_init()
30 tmp = readl(SC_VPLL27ACTRL); in vpll_init()
31 tmp |= 0x00000001; in vpll_init()
32 writel(tmp, SC_VPLL27ACTRL); in vpll_init()
33 tmp = readl(SC_VPLL27BCTRL); in vpll_init()
34 tmp |= 0x00000001; in vpll_init()
35 writel(tmp, SC_VPLL27BCTRL); in vpll_init()
38 tmp = readl(SC_VPLL27ACTRL3); in vpll_init()
[all …]
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| /OK3568_Linux_fs/buildroot/dl/sox/git/src/ |
| H A D | test-comments | 3 tmp=/tmp/`basename $0`-$$
4 input=$tmp.wav # no comment support
7 ./sox --i -a $1 > $tmp.comments
8 cmp $tmp.comments $2 || exit 1
13 : > $tmp.expected
15 echo "$1" >> $tmp.expected
18 check_file $f $tmp.expected
27 ./sox $input $tmp.au # Apply default comment
28 check $tmp.au "$com0"
30 cp $tmp.au $tmp.comment.au
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfxhub_v1_0.c | 121 uint32_t tmp; in gfxhub_v1_0_init_tlb_regs() local
124 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_0_init_tlb_regs()
126 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
127 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v1_0_init_tlb_regs()
128 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
130 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
132 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v1_0_init_tlb_regs()
133 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
135 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in gfxhub_v1_0_init_tlb_regs()
137 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_0_init_tlb_regs()
[all …]
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| H A D | gfxhub_v2_0.c | 189 uint32_t tmp; in gfxhub_v2_0_init_tlb_regs() local
192 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_0_init_tlb_regs()
194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v2_0_init_tlb_regs()
196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs()
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs()
200 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v2_0_init_tlb_regs()
201 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs()
204 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_0_init_tlb_regs()
209 uint32_t tmp; in gfxhub_v2_0_init_cache_regs() local
[all …]
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| H A D | gfxhub_v2_1.c | 187 uint32_t tmp; in gfxhub_v2_1_init_tlb_regs() local
190 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_init_tlb_regs()
192 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_1_init_tlb_regs()
193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v2_1_init_tlb_regs()
194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_1_init_tlb_regs()
196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_1_init_tlb_regs()
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v2_1_init_tlb_regs()
199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_1_init_tlb_regs()
202 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_1_init_tlb_regs()
207 uint32_t tmp; in gfxhub_v2_1_init_cache_regs() local
[all …]
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| H A D | mmhub_v2_0.c | 196 uint32_t tmp; in mmhub_v2_0_init_system_aperture_regs() local
225 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_0_init_system_aperture_regs()
226 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v2_0_init_system_aperture_regs()
228 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v2_0_init_system_aperture_regs()
233 uint32_t tmp; in mmhub_v2_0_init_tlb_regs() local
236 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_init_tlb_regs()
238 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_0_init_tlb_regs()
239 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v2_0_init_tlb_regs()
240 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v2_0_init_tlb_regs()
242 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v2_0_init_tlb_regs()
[all …]
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| H A D | mmhub_v1_0.c | 88 uint32_t tmp; in mmhub_v1_0_init_system_aperture_regs() local
130 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v1_0_init_system_aperture_regs()
131 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v1_0_init_system_aperture_regs()
133 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v1_0_init_system_aperture_regs()
138 uint32_t tmp; in mmhub_v1_0_init_tlb_regs() local
141 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_init_tlb_regs()
143 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v1_0_init_tlb_regs()
145 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
147 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
[all …]
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| H A D | gmc_v8_0.c | 199 u32 tmp; in gmc_v8_0_mc_resume() local
202 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_resume()
203 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v8_0_mc_resume()
204 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v8_0_mc_resume()
206 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v8_0_mc_resume()
207 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); in gmc_v8_0_mc_resume()
208 WREG32(mmBIF_FB_EN, tmp); in gmc_v8_0_mc_resume()
453 u32 tmp; in gmc_v8_0_mc_program() local
471 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v8_0_mc_program()
472 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v8_0_mc_program()
[all …]
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| H A D | gmc_v7_0.c | 111 u32 tmp; in gmc_v7_0_mc_resume() local
114 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_resume()
115 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v7_0_mc_resume()
116 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v7_0_mc_resume()
118 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v7_0_mc_resume()
119 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); in gmc_v7_0_mc_resume()
120 WREG32(mmBIF_FB_EN, tmp); in gmc_v7_0_mc_resume()
262 u32 tmp; in gmc_v7_0_mc_program() local
280 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v7_0_mc_program()
281 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v7_0_mc_program()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/ |
| H A D | radeon_clocks.c | 200 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); in radeon_get_clock_info() local
203 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; in radeon_get_clock_info()
205 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; in radeon_get_clock_info()
393 uint32_t tmp; in radeon_legacy_set_engine_clock() local
400 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_engine_clock()
401 tmp &= ~RADEON_DONT_USE_XTALIN; in radeon_legacy_set_engine_clock()
402 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
404 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()
405 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_set_engine_clock()
406 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
[all …]
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| H A D | vce_v2_0.c | 40 u32 tmp; in vce_v2_0_set_sw_cg() local
43 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
44 tmp |= 0xe70000; in vce_v2_0_set_sw_cg()
45 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
47 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
48 tmp |= 0xff000000; in vce_v2_0_set_sw_cg()
49 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
51 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
52 tmp &= ~0x3fc; in vce_v2_0_set_sw_cg()
53 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/phy/mediatek/ |
| H A D | phy-mtk-tphy.c | 331 u32 tmp; in hs_slew_rate_calibrate() local
338 tmp = readl(com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
339 tmp |= PA5_RG_U2_HSTX_SRCAL_EN; in hs_slew_rate_calibrate()
340 writel(tmp, com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
344 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
345 tmp |= P2F_RG_FRCK_EN; in hs_slew_rate_calibrate()
346 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
349 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
350 tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL); in hs_slew_rate_calibrate()
351 tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT); in hs_slew_rate_calibrate()
[all …]
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| H A D | phy-mtk-xsphy.c | 122 u32 tmp; in u2_phy_slew_rate_calibrate() local
129 tmp = readl(pbase + XSP_USBPHYACR5); in u2_phy_slew_rate_calibrate()
130 tmp |= P2A5_RG_HSTX_SRCAL_EN; in u2_phy_slew_rate_calibrate()
131 writel(tmp, pbase + XSP_USBPHYACR5); in u2_phy_slew_rate_calibrate()
135 tmp = readl(pbase + XSP_U2FREQ_FMMONR1); in u2_phy_slew_rate_calibrate()
136 tmp |= P2F_RG_FRCK_EN; in u2_phy_slew_rate_calibrate()
137 writel(tmp, pbase + XSP_U2FREQ_FMMONR1); in u2_phy_slew_rate_calibrate()
140 tmp = readl(pbase + XSP_U2FREQ_FMCR0); in u2_phy_slew_rate_calibrate()
141 tmp &= ~(P2F_RG_CYCLECNT); in u2_phy_slew_rate_calibrate()
142 tmp |= P2F_RG_CYCLECNT_VAL(XSP_FM_DET_CYCLE_CNT); in u2_phy_slew_rate_calibrate()
[all …]
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| /OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | mpc8536_serdes.c | 96 u32 tmp; in fsl_serdes_init() local
116 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
117 tmp &= ~FSL_SRDSCR0_TXEQA_MASK; in fsl_serdes_init()
118 tmp |= FSL_SRDSCR0_TXEQA_SATA; in fsl_serdes_init()
119 tmp &= ~FSL_SRDSCR0_TXEQE_MASK; in fsl_serdes_init()
120 tmp |= FSL_SRDSCR0_TXEQE_SATA; in fsl_serdes_init()
121 out_be32(sd + FSL_SRDSCR0_OFFS, tmp); in fsl_serdes_init()
123 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
124 tmp &= ~FSL_SRDSCR1_LANEA_MASK; in fsl_serdes_init()
125 tmp &= ~FSL_SRDSCR1_LANEE_MASK; in fsl_serdes_init()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/scsi/mvsas/ |
| H A D | mv_64xx.c | 31 u32 tmp; in mvs_64xx_enable_xmt() local
33 tmp = mr32(MVS_PCS); in mvs_64xx_enable_xmt()
35 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT); in mvs_64xx_enable_xmt()
37 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); in mvs_64xx_enable_xmt()
38 mw32(MVS_PCS, tmp); in mvs_64xx_enable_xmt()
70 u32 reg, tmp; in mvs_64xx_stp_reset() local
81 tmp = reg; in mvs_64xx_stp_reset()
83 tmp |= (1U << phy_id) << PCTL_LINK_OFFS; in mvs_64xx_stp_reset()
85 tmp |= (1U << (phy_id - MVS_SOC_PORTS)) << PCTL_LINK_OFFS; in mvs_64xx_stp_reset()
89 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); in mvs_64xx_stp_reset()
[all …]
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| H A D | mv_94xx.c | 38 u32 tmp, setting_0 = 0, setting_1 = 0; in set_phy_tuning() local
81 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_tuning()
82 tmp &= ~(0xFBE << 16); in set_phy_tuning()
83 tmp |= (((phy_tuning.trans_emp_en << 11) | in set_phy_tuning()
86 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_tuning()
90 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_tuning()
91 tmp &= ~(0xC000); in set_phy_tuning()
92 tmp |= (phy_tuning.trans_amp_adj << 14); in set_phy_tuning()
93 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_tuning()
100 u32 tmp; in set_phy_ffe_tuning() local
[all …]
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| /OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc83xx/ |
| H A D | serdes.c | 49 u32 tmp; in fsl_setup_serdes() local
54 tmp = in_be32(regs + FSL_SRDSCR0_OFFS); in fsl_setup_serdes()
55 tmp &= ~FSL_SRDSCR0_DPP_1V2; in fsl_setup_serdes()
56 out_be32(regs + FSL_SRDSCR0_OFFS, tmp); in fsl_setup_serdes()
59 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
60 tmp &= ~FSL_SRDSCR2_VDD_1V2; in fsl_setup_serdes()
61 out_be32(regs + FSL_SRDSCR2_OFFS, tmp); in fsl_setup_serdes()
68 tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); in fsl_setup_serdes()
69 tmp |= FSL_SRDSRSTCTL_SATA_RESET; in fsl_setup_serdes()
70 out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); in fsl_setup_serdes()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/staging/fbtft/ |
| H A D | fb_ssd1331.c | 133 unsigned long tmp[GAMMA_NUM * GAMMA_LEN]; in set_gamma() local
144 tmp[i] = acc; in set_gamma()
154 tmp[0], tmp[1], tmp[2], tmp[3], tmp[4], tmp[5], tmp[6], in set_gamma()
155 tmp[7], tmp[8], tmp[9], tmp[10], tmp[11], tmp[12], tmp[13], in set_gamma()
156 tmp[14], tmp[15], tmp[16], tmp[17], tmp[18], tmp[19], tmp[20], in set_gamma()
157 tmp[21], tmp[22], tmp[23], tmp[24], tmp[25], tmp[26], tmp[27], in set_gamma()
158 tmp[28], tmp[29], tmp[30], tmp[31], tmp[32], tmp[33], tmp[34], in set_gamma()
159 tmp[35], tmp[36], tmp[37], tmp[38], tmp[39], tmp[40], tmp[41], in set_gamma()
160 tmp[42], tmp[43], tmp[44], tmp[45], tmp[46], tmp[47], tmp[48], in set_gamma()
161 tmp[49], tmp[50], tmp[51], tmp[52], tmp[53], tmp[54], tmp[55], in set_gamma()
[all …]
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| H A D | fb_ssd1351.c | 122 unsigned long tmp[GAMMA_NUM * GAMMA_LEN]; in set_gamma() local
133 tmp[i] = acc; in set_gamma()
143 tmp[0], tmp[1], tmp[2], tmp[3], in set_gamma()
144 tmp[4], tmp[5], tmp[6], tmp[7], in set_gamma()
145 tmp[8], tmp[9], tmp[10], tmp[11], in set_gamma()
146 tmp[12], tmp[13], tmp[14], tmp[15], in set_gamma()
147 tmp[16], tmp[17], tmp[18], tmp[19], in set_gamma()
148 tmp[20], tmp[21], tmp[22], tmp[23], in set_gamma()
149 tmp[24], tmp[25], tmp[26], tmp[27], in set_gamma()
150 tmp[28], tmp[29], tmp[30], tmp[31], in set_gamma()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/ |
| H A D | dma.c | 29 hrt_data tmp; in dma_get_state() local
34 tmp = dma_reg_load(ID, DMA_COMMAND_FSM_REG_IDX); in dma_get_state()
39 state->fsm_command_idle = tmp & 0x1; in dma_get_state()
40 state->fsm_command_run = tmp & 0x2; in dma_get_state()
41 state->fsm_command_stalling = tmp & 0x4; in dma_get_state()
42 state->fsm_command_error = tmp & 0x8; in dma_get_state()
43 state->last_command_channel = (tmp >> 10 & 0x1F); in dma_get_state()
44 state->last_command_param = (tmp >> 15 & 0x0F); in dma_get_state()
45 tmp = (tmp >> 4) & 0x3F; in dma_get_state()
46 /* state->last_command = (dma_commands_t)tmp; */ in dma_get_state()
[all …]
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| /OK3568_Linux_fs/kernel/fs/ |
| H A D | stat.c | 228 struct __old_kernel_stat tmp; in cp_old_stat() local
239 memset(&tmp, 0, sizeof(struct __old_kernel_stat)); in cp_old_stat()
240 tmp.st_dev = old_encode_dev(stat->dev); in cp_old_stat()
241 tmp.st_ino = stat->ino; in cp_old_stat()
242 if (sizeof(tmp.st_ino) < sizeof(stat->ino) && tmp.st_ino != stat->ino) in cp_old_stat()
244 tmp.st_mode = stat->mode; in cp_old_stat()
245 tmp.st_nlink = stat->nlink; in cp_old_stat()
246 if (tmp.st_nlink != stat->nlink) in cp_old_stat()
248 SET_UID(tmp.st_uid, from_kuid_munged(current_user_ns(), stat->uid)); in cp_old_stat()
249 SET_GID(tmp.st_gid, from_kgid_munged(current_user_ns(), stat->gid)); in cp_old_stat()
[all …]
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| /OK3568_Linux_fs/kernel/arch/csky/kernel/probes/ |
| H A D | simulate-insn.c | 125 unsigned long tmp = (opcode >> 2) & 0xf; in simulate_jmp16() local
127 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_jmp16()
129 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jmp16()
135 unsigned long tmp = opcode & 0x1f; in simulate_jmp32() local
137 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_jmp32()
139 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jmp32()
145 unsigned long tmp = (opcode >> 2) & 0xf; in simulate_jsr16() local
147 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_jsr16()
151 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jsr16()
157 unsigned long tmp = opcode & 0x1f; in simulate_jsr32() local
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| /OK3568_Linux_fs/kernel/arch/alpha/math-emu/ |
| H A D | qrnnd.S | 41 #define tmp $3 macro
52 $loop1: cmplt n0,0,tmp
54 bis n1,tmp,n1
57 subq n1,d,tmp
58 cmovne qb,tmp,n1
60 cmplt n0,0,tmp
62 bis n1,tmp,n1
65 subq n1,d,tmp
66 cmovne qb,tmp,n1
68 cmplt n0,0,tmp
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/ |
| H A D | icl_dsi.c | 129 u32 tmp = 0; in add_payld_to_queue() local
139 tmp |= *data++ << 8 * j; in add_payld_to_queue()
141 intel_de_write(dev_priv, DSI_CMD_TXPYLD(dsi_trans), tmp); in add_payld_to_queue()
153 u32 tmp; in dsi_send_pkt_hdr() local
164 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); in dsi_send_pkt_hdr()
167 tmp |= PAYLOAD_PRESENT; in dsi_send_pkt_hdr()
169 tmp &= ~PAYLOAD_PRESENT; in dsi_send_pkt_hdr()
171 tmp &= ~VBLANK_FENCE; in dsi_send_pkt_hdr()
174 tmp |= LP_DATA_TRANSFER; in dsi_send_pkt_hdr()
176 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); in dsi_send_pkt_hdr()
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