1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2013-2014 Panasonic Corporation
3*4882a593Smuzhiyun * Copyright (C) 2015-2016 Socionext Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/delay.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "../init.h"
12*4882a593Smuzhiyun #include "../sc-regs.h"
13*4882a593Smuzhiyun #include "../sg-regs.h"
14*4882a593Smuzhiyun #include "pll.h"
15*4882a593Smuzhiyun
upll_init(void)16*4882a593Smuzhiyun static void upll_init(void)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun u32 tmp, clk_mode_upll, clk_mode_axosel;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun tmp = readl(SG_PINMON0);
21*4882a593Smuzhiyun clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
22*4882a593Smuzhiyun clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
25*4882a593Smuzhiyun tmp = readl(SC_UPLLCTRL);
26*4882a593Smuzhiyun tmp &= ~0x18000000;
27*4882a593Smuzhiyun writel(tmp, SC_UPLLCTRL);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
30*4882a593Smuzhiyun if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
31*4882a593Smuzhiyun clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
32*4882a593Smuzhiyun /* AXO: 25MHz */
33*4882a593Smuzhiyun tmp &= ~0x07ffffff;
34*4882a593Smuzhiyun tmp |= 0x0228f5c0;
35*4882a593Smuzhiyun } else {
36*4882a593Smuzhiyun /* AXO: default 24.576MHz */
37*4882a593Smuzhiyun tmp &= ~0x07ffffff;
38*4882a593Smuzhiyun tmp |= 0x02328000;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun writel(tmp, SC_UPLLCTRL);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* set 1 to K_LD(UPLLCTRL.bit[27]) */
45*4882a593Smuzhiyun tmp |= 0x08000000;
46*4882a593Smuzhiyun writel(tmp, SC_UPLLCTRL);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* wait 10 usec */
49*4882a593Smuzhiyun udelay(10);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* set 1 to SNRT(UPLLCTRL.bit[28]) */
52*4882a593Smuzhiyun tmp |= 0x10000000;
53*4882a593Smuzhiyun writel(tmp, SC_UPLLCTRL);
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
vpll_init(void)56*4882a593Smuzhiyun static void vpll_init(void)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun u32 tmp, clk_mode_axosel;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun tmp = readl(SG_PINMON0);
61*4882a593Smuzhiyun clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* set 1 to VPLA27WP and VPLA27WP */
64*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL);
65*4882a593Smuzhiyun tmp |= 0x00000001;
66*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL);
67*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL);
68*4882a593Smuzhiyun tmp |= 0x00000001;
69*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* Set 0 to VPLA_K_LD and VPLB_K_LD */
72*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL3);
73*4882a593Smuzhiyun tmp &= ~0x10000000;
74*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL3);
75*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL3);
76*4882a593Smuzhiyun tmp &= ~0x10000000;
77*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL3);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* Set 0 to VPLA_SNRST and VPLB_SNRST */
80*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL2);
81*4882a593Smuzhiyun tmp &= ~0x10000000;
82*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL2);
83*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL2);
84*4882a593Smuzhiyun tmp &= ~0x10000000;
85*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL2);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
88*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL2);
89*4882a593Smuzhiyun tmp &= ~0x0000007f;
90*4882a593Smuzhiyun tmp |= 0x00000020;
91*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL2);
92*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL2);
93*4882a593Smuzhiyun tmp &= ~0x0000007f;
94*4882a593Smuzhiyun tmp |= 0x00000020;
95*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL2);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
98*4882a593Smuzhiyun clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
99*4882a593Smuzhiyun /* AXO: 25MHz */
100*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL3);
101*4882a593Smuzhiyun tmp &= ~0x000fffff;
102*4882a593Smuzhiyun tmp |= 0x00066664;
103*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL3);
104*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL3);
105*4882a593Smuzhiyun tmp &= ~0x000fffff;
106*4882a593Smuzhiyun tmp |= 0x00066664;
107*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL3);
108*4882a593Smuzhiyun } else {
109*4882a593Smuzhiyun /* AXO: default 24.576MHz */
110*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL3);
111*4882a593Smuzhiyun tmp &= ~0x000fffff;
112*4882a593Smuzhiyun tmp |= 0x000f5800;
113*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL3);
114*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL3);
115*4882a593Smuzhiyun tmp &= ~0x000fffff;
116*4882a593Smuzhiyun tmp |= 0x000f5800;
117*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL3);
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* Set 1 to VPLA_K_LD and VPLB_K_LD */
121*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL3);
122*4882a593Smuzhiyun tmp |= 0x10000000;
123*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL3);
124*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL3);
125*4882a593Smuzhiyun tmp |= 0x10000000;
126*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL3);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /* wait 10 usec */
129*4882a593Smuzhiyun udelay(10);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* Set 0 to VPLA_SNRST and VPLB_SNRST */
132*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL2);
133*4882a593Smuzhiyun tmp |= 0x10000000;
134*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL2);
135*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL2);
136*4882a593Smuzhiyun tmp |= 0x10000000;
137*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL2);
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun /* set 0 to VPLA27WP and VPLA27WP */
140*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL);
141*4882a593Smuzhiyun tmp &= ~0x00000001;
142*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL);
143*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL);
144*4882a593Smuzhiyun tmp |= ~0x00000001;
145*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL);
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
uniphier_ld4_pll_init(void)148*4882a593Smuzhiyun void uniphier_ld4_pll_init(void)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun upll_init();
151*4882a593Smuzhiyun vpll_init();
152*4882a593Smuzhiyun uniphier_ld4_dpll_ssc_en();
153*4882a593Smuzhiyun }
154