Lines Matching full:tmp
331 u32 tmp; in hs_slew_rate_calibrate() local
338 tmp = readl(com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
339 tmp |= PA5_RG_U2_HSTX_SRCAL_EN; in hs_slew_rate_calibrate()
340 writel(tmp, com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
344 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
345 tmp |= P2F_RG_FRCK_EN; in hs_slew_rate_calibrate()
346 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
349 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
350 tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL); in hs_slew_rate_calibrate()
351 tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT); in hs_slew_rate_calibrate()
353 tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1); in hs_slew_rate_calibrate()
355 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
358 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
359 tmp |= P2F_RG_FREQDET_EN; in hs_slew_rate_calibrate()
360 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
363 readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp, in hs_slew_rate_calibrate()
364 (tmp & P2F_USB_FM_VALID), 10, 200); in hs_slew_rate_calibrate()
369 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
370 tmp &= ~P2F_RG_FREQDET_EN; in hs_slew_rate_calibrate()
371 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
374 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
375 tmp &= ~P2F_RG_FRCK_EN; in hs_slew_rate_calibrate()
376 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
380 tmp = tphy->src_ref_clk * tphy->src_coef; in hs_slew_rate_calibrate()
381 tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out; in hs_slew_rate_calibrate()
382 calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR); in hs_slew_rate_calibrate()
392 tmp = readl(com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
393 tmp &= ~PA5_RG_U2_HSTX_SRCTRL; in hs_slew_rate_calibrate()
394 tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val); in hs_slew_rate_calibrate()
395 writel(tmp, com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
398 tmp = readl(com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
399 tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN; in hs_slew_rate_calibrate()
400 writel(tmp, com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
407 u32 tmp; in u3_phy_instance_init() local
410 tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3); in u3_phy_instance_init()
411 tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD; in u3_phy_instance_init()
412 writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3); in u3_phy_instance_init()
415 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); in u3_phy_instance_init()
416 tmp &= ~P3A_RG_XTAL_EXT_EN_U3; in u3_phy_instance_init()
417 tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2); in u3_phy_instance_init()
418 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); in u3_phy_instance_init()
420 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9); in u3_phy_instance_init()
421 tmp &= ~P3A_RG_RX_DAC_MUX; in u3_phy_instance_init()
422 tmp |= P3A_RG_RX_DAC_MUX_VAL(4); in u3_phy_instance_init()
423 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9); in u3_phy_instance_init()
425 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6); in u3_phy_instance_init()
426 tmp &= ~P3A_RG_TX_EIDLE_CM; in u3_phy_instance_init()
427 tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe); in u3_phy_instance_init()
428 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6); in u3_phy_instance_init()
430 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1); in u3_phy_instance_init()
431 tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1); in u3_phy_instance_init()
432 tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3); in u3_phy_instance_init()
433 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1); in u3_phy_instance_init()
435 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1); in u3_phy_instance_init()
436 tmp &= ~P3D_RG_FWAKE_TH; in u3_phy_instance_init()
437 tmp |= P3D_RG_FWAKE_TH_VAL(0x34); in u3_phy_instance_init()
438 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1); in u3_phy_instance_init()
440 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); in u3_phy_instance_init()
441 tmp &= ~P3D_RG_RXDET_STB2_SET; in u3_phy_instance_init()
442 tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); in u3_phy_instance_init()
443 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); in u3_phy_instance_init()
445 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); in u3_phy_instance_init()
446 tmp &= ~P3D_RG_RXDET_STB2_SET_P3; in u3_phy_instance_init()
447 tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); in u3_phy_instance_init()
448 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); in u3_phy_instance_init()
459 u32 tmp; in u2_phy_instance_init() local
462 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_init()
463 tmp &= ~(P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM); in u2_phy_instance_init()
464 tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0); in u2_phy_instance_init()
465 writel(tmp, com + U3P_U2PHYDTM0); in u2_phy_instance_init()
467 tmp = readl(com + U3P_U2PHYDTM1); in u2_phy_instance_init()
468 tmp &= ~P2C_RG_UART_EN; in u2_phy_instance_init()
469 writel(tmp, com + U3P_U2PHYDTM1); in u2_phy_instance_init()
471 tmp = readl(com + U3P_USBPHYACR0); in u2_phy_instance_init()
472 tmp |= PA0_RG_USB20_INTR_EN; in u2_phy_instance_init()
473 writel(tmp, com + U3P_USBPHYACR0); in u2_phy_instance_init()
476 tmp = readl(com + U3P_USBPHYACR5); in u2_phy_instance_init()
477 tmp &= ~PA5_RG_U2_HS_100U_U3_EN; in u2_phy_instance_init()
478 writel(tmp, com + U3P_USBPHYACR5); in u2_phy_instance_init()
481 tmp = readl(com + U3P_U2PHYACR4); in u2_phy_instance_init()
482 tmp &= ~P2C_U2_GPIO_CTR_MSK; in u2_phy_instance_init()
483 writel(tmp, com + U3P_U2PHYACR4); in u2_phy_instance_init()
488 tmp = readl(com + U3P_USBPHYACR2); in u2_phy_instance_init()
489 tmp |= PA2_RG_SIF_U2PLL_FORCE_EN; in u2_phy_instance_init()
490 writel(tmp, com + U3P_USBPHYACR2); in u2_phy_instance_init()
492 tmp = readl(com + U3D_U2PHYDCR0); in u2_phy_instance_init()
493 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; in u2_phy_instance_init()
494 writel(tmp, com + U3D_U2PHYDCR0); in u2_phy_instance_init()
496 tmp = readl(com + U3D_U2PHYDCR0); in u2_phy_instance_init()
497 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; in u2_phy_instance_init()
498 writel(tmp, com + U3D_U2PHYDCR0); in u2_phy_instance_init()
500 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_init()
501 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; in u2_phy_instance_init()
502 writel(tmp, com + U3P_U2PHYDTM0); in u2_phy_instance_init()
506 tmp = readl(com + U3P_USBPHYACR6); in u2_phy_instance_init()
507 tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */ in u2_phy_instance_init()
508 tmp &= ~PA6_RG_U2_SQTH; in u2_phy_instance_init()
509 tmp |= PA6_RG_U2_SQTH_VAL(2); in u2_phy_instance_init()
510 writel(tmp, com + U3P_USBPHYACR6); in u2_phy_instance_init()
521 u32 tmp; in u2_phy_instance_power_on() local
523 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_power_on()
524 tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); in u2_phy_instance_power_on()
525 writel(tmp, com + U3P_U2PHYDTM0); in u2_phy_instance_power_on()
528 tmp = readl(com + U3P_USBPHYACR6); in u2_phy_instance_power_on()
529 tmp |= PA6_RG_U2_OTG_VBUSCMP_EN; in u2_phy_instance_power_on()
530 writel(tmp, com + U3P_USBPHYACR6); in u2_phy_instance_power_on()
532 tmp = readl(com + U3P_U2PHYDTM1); in u2_phy_instance_power_on()
533 tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID; in u2_phy_instance_power_on()
534 tmp &= ~P2C_RG_SESSEND; in u2_phy_instance_power_on()
535 writel(tmp, com + U3P_U2PHYDTM1); in u2_phy_instance_power_on()
538 tmp = readl(com + U3D_U2PHYDCR0); in u2_phy_instance_power_on()
539 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; in u2_phy_instance_power_on()
540 writel(tmp, com + U3D_U2PHYDCR0); in u2_phy_instance_power_on()
542 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_power_on()
543 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; in u2_phy_instance_power_on()
544 writel(tmp, com + U3P_U2PHYDTM0); in u2_phy_instance_power_on()
555 u32 tmp; in u2_phy_instance_power_off() local
557 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_power_off()
558 tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN); in u2_phy_instance_power_off()
559 writel(tmp, com + U3P_U2PHYDTM0); in u2_phy_instance_power_off()
562 tmp = readl(com + U3P_USBPHYACR6); in u2_phy_instance_power_off()
563 tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN; in u2_phy_instance_power_off()
564 writel(tmp, com + U3P_USBPHYACR6); in u2_phy_instance_power_off()
566 tmp = readl(com + U3P_U2PHYDTM1); in u2_phy_instance_power_off()
567 tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID); in u2_phy_instance_power_off()
568 tmp |= P2C_RG_SESSEND; in u2_phy_instance_power_off()
569 writel(tmp, com + U3P_U2PHYDTM1); in u2_phy_instance_power_off()
572 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_power_off()
573 tmp &= ~(P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM); in u2_phy_instance_power_off()
574 writel(tmp, com + U3P_U2PHYDTM0); in u2_phy_instance_power_off()
576 tmp = readl(com + U3D_U2PHYDCR0); in u2_phy_instance_power_off()
577 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; in u2_phy_instance_power_off()
578 writel(tmp, com + U3D_U2PHYDCR0); in u2_phy_instance_power_off()
590 u32 tmp; in u2_phy_instance_exit() local
593 tmp = readl(com + U3D_U2PHYDCR0); in u2_phy_instance_exit()
594 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; in u2_phy_instance_exit()
595 writel(tmp, com + U3D_U2PHYDCR0); in u2_phy_instance_exit()
597 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_exit()
598 tmp &= ~P2C_FORCE_SUSPENDM; in u2_phy_instance_exit()
599 writel(tmp, com + U3P_U2PHYDTM0); in u2_phy_instance_exit()
608 u32 tmp; in u2_phy_instance_set_mode() local
610 tmp = readl(u2_banks->com + U3P_U2PHYDTM1); in u2_phy_instance_set_mode()
613 tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG; in u2_phy_instance_set_mode()
616 tmp |= P2C_FORCE_IDDIG; in u2_phy_instance_set_mode()
617 tmp &= ~P2C_RG_IDDIG; in u2_phy_instance_set_mode()
620 tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG); in u2_phy_instance_set_mode()
625 writel(tmp, u2_banks->com + U3P_U2PHYDTM1); in u2_phy_instance_set_mode()
632 u32 tmp; in pcie_phy_instance_init() local
637 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); in pcie_phy_instance_init()
638 tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H); in pcie_phy_instance_init()
639 tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2); in pcie_phy_instance_init()
640 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); in pcie_phy_instance_init()
643 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1); in pcie_phy_instance_init()
644 tmp &= ~P3A_RG_CLKDRV_AMP; in pcie_phy_instance_init()
645 tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4); in pcie_phy_instance_init()
646 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1); in pcie_phy_instance_init()
648 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); in pcie_phy_instance_init()
649 tmp &= ~P3A_RG_CLKDRV_OFF; in pcie_phy_instance_init()
650 tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1); in pcie_phy_instance_init()
651 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); in pcie_phy_instance_init()
654 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20); in pcie_phy_instance_init()
655 tmp &= ~P3A_RG_PLL_DELTA1_PE2H; in pcie_phy_instance_init()
656 tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c); in pcie_phy_instance_init()
657 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20); in pcie_phy_instance_init()
659 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25); in pcie_phy_instance_init()
660 tmp &= ~P3A_RG_PLL_DELTA_PE2H; in pcie_phy_instance_init()
661 tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36); in pcie_phy_instance_init()
662 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25); in pcie_phy_instance_init()
665 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5); in pcie_phy_instance_init()
666 tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H); in pcie_phy_instance_init()
667 tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1); in pcie_phy_instance_init()
668 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5); in pcie_phy_instance_init()
670 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4); in pcie_phy_instance_init()
671 tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H); in pcie_phy_instance_init()
672 tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3); in pcie_phy_instance_init()
673 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4); in pcie_phy_instance_init()
675 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6); in pcie_phy_instance_init()
676 tmp &= ~P3A_RG_PLL_IR_PE2H; in pcie_phy_instance_init()
677 tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2); in pcie_phy_instance_init()
678 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6); in pcie_phy_instance_init()
680 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7); in pcie_phy_instance_init()
681 tmp &= ~P3A_RG_PLL_BP_PE2H; in pcie_phy_instance_init()
682 tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa); in pcie_phy_instance_init()
683 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7); in pcie_phy_instance_init()
686 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); in pcie_phy_instance_init()
687 tmp &= ~P3D_RG_RXDET_STB2_SET; in pcie_phy_instance_init()
688 tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); in pcie_phy_instance_init()
689 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); in pcie_phy_instance_init()
691 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); in pcie_phy_instance_init()
692 tmp &= ~P3D_RG_RXDET_STB2_SET_P3; in pcie_phy_instance_init()
693 tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); in pcie_phy_instance_init()
694 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); in pcie_phy_instance_init()
705 u32 tmp; in pcie_phy_instance_power_on() local
707 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); in pcie_phy_instance_power_on()
708 tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST); in pcie_phy_instance_power_on()
709 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); in pcie_phy_instance_power_on()
711 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); in pcie_phy_instance_power_on()
712 tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); in pcie_phy_instance_power_on()
713 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); in pcie_phy_instance_power_on()
721 u32 tmp; in pcie_phy_instance_power_off() local
723 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); in pcie_phy_instance_power_off()
724 tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST; in pcie_phy_instance_power_off()
725 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); in pcie_phy_instance_power_off()
727 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); in pcie_phy_instance_power_off()
728 tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD; in pcie_phy_instance_power_off()
729 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); in pcie_phy_instance_power_off()
737 u32 tmp; in sata_phy_instance_init() local
740 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6); in sata_phy_instance_init()
741 tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK); in sata_phy_instance_init()
742 tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a); in sata_phy_instance_init()
743 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6); in sata_phy_instance_init()
745 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4); in sata_phy_instance_init()
746 tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK; in sata_phy_instance_init()
747 tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18); in sata_phy_instance_init()
748 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4); in sata_phy_instance_init()
750 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5); in sata_phy_instance_init()
751 tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK; in sata_phy_instance_init()
752 tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06); in sata_phy_instance_init()
753 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5); in sata_phy_instance_init()
755 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4); in sata_phy_instance_init()
756 tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK); in sata_phy_instance_init()
757 tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07); in sata_phy_instance_init()
758 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4); in sata_phy_instance_init()
760 tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4); in sata_phy_instance_init()
761 tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK); in sata_phy_instance_init()
762 tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02); in sata_phy_instance_init()
763 writel(tmp, phyd + PHYD_CTRL_SIGNAL_MODE4); in sata_phy_instance_init()
765 tmp = readl(phyd + PHYD_DESIGN_OPTION2); in sata_phy_instance_init()
766 tmp &= ~RG_LOCK_CNT_SEL_MSK; in sata_phy_instance_init()
767 tmp |= RG_LOCK_CNT_SEL_VAL(0x02); in sata_phy_instance_init()
768 writel(tmp, phyd + PHYD_DESIGN_OPTION2); in sata_phy_instance_init()
770 tmp = readl(phyd + PHYD_DESIGN_OPTION9); in sata_phy_instance_init()
771 tmp &= ~(RG_T2_MIN_MSK | RG_TG_MIN_MSK | in sata_phy_instance_init()
773 tmp |= RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) | in sata_phy_instance_init()
775 writel(tmp, phyd + PHYD_DESIGN_OPTION9); in sata_phy_instance_init()
777 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL1); in sata_phy_instance_init()
778 tmp &= ~RG_IDRV_0DB_GEN1_MSK; in sata_phy_instance_init()
779 tmp |= RG_IDRV_0DB_GEN1_VAL(0x20); in sata_phy_instance_init()
780 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL1); in sata_phy_instance_init()
782 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL1); in sata_phy_instance_init()
783 tmp &= ~RG_EQ_DLEQ_LFI_GEN1_MSK; in sata_phy_instance_init()
784 tmp |= RG_EQ_DLEQ_LFI_GEN1_VAL(0x03); in sata_phy_instance_init()
785 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL1); in sata_phy_instance_init()
873 u32 tmp; in u2_phy_props_set() local
876 tmp = readl(com + U3P_U2PHYBC12C); in u2_phy_props_set()
877 tmp |= P2C_RG_CHGDT_EN; /* BC1.2 path Enable */ in u2_phy_props_set()
878 writel(tmp, com + U3P_U2PHYBC12C); in u2_phy_props_set()
882 tmp = readl(com + U3P_USBPHYACR5); in u2_phy_props_set()
883 tmp &= ~PA5_RG_U2_HSTX_SRCTRL; in u2_phy_props_set()
884 tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src); in u2_phy_props_set()
885 writel(tmp, com + U3P_USBPHYACR5); in u2_phy_props_set()
889 tmp = readl(com + U3P_USBPHYACR1); in u2_phy_props_set()
890 tmp &= ~PA1_RG_VRT_SEL; in u2_phy_props_set()
891 tmp |= PA1_RG_VRT_SEL_VAL(instance->eye_vrt); in u2_phy_props_set()
892 writel(tmp, com + U3P_USBPHYACR1); in u2_phy_props_set()
896 tmp = readl(com + U3P_USBPHYACR1); in u2_phy_props_set()
897 tmp &= ~PA1_RG_TERM_SEL; in u2_phy_props_set()
898 tmp |= PA1_RG_TERM_SEL_VAL(instance->eye_term); in u2_phy_props_set()
899 writel(tmp, com + U3P_USBPHYACR1); in u2_phy_props_set()
903 tmp = readl(com + U3P_USBPHYACR1); in u2_phy_props_set()
904 tmp &= ~PA1_RG_INTR_CAL; in u2_phy_props_set()
905 tmp |= PA1_RG_INTR_CAL_VAL(instance->intr); in u2_phy_props_set()
906 writel(tmp, com + U3P_USBPHYACR1); in u2_phy_props_set()
910 tmp = readl(com + U3P_USBPHYACR6); in u2_phy_props_set()
911 tmp &= ~PA6_RG_U2_DISCTH; in u2_phy_props_set()
912 tmp |= PA6_RG_U2_DISCTH_VAL(instance->discth); in u2_phy_props_set()
913 writel(tmp, com + U3P_USBPHYACR6); in u2_phy_props_set()