1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2013-2014 Panasonic Corporation
3*4882a593Smuzhiyun * Copyright (C) 2015-2016 Socionext Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/delay.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "../init.h"
12*4882a593Smuzhiyun #include "../sc-regs.h"
13*4882a593Smuzhiyun #include "../sg-regs.h"
14*4882a593Smuzhiyun #include "pll.h"
15*4882a593Smuzhiyun
vpll_init(void)16*4882a593Smuzhiyun static void vpll_init(void)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun u32 tmp, clk_mode_axosel;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* Set VPLL27A & VPLL27B */
21*4882a593Smuzhiyun tmp = readl(SG_PINMON0);
22*4882a593Smuzhiyun clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
25*4882a593Smuzhiyun if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
26*4882a593Smuzhiyun clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
27*4882a593Smuzhiyun return;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
30*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL);
31*4882a593Smuzhiyun tmp |= 0x00000001;
32*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL);
33*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL);
34*4882a593Smuzhiyun tmp |= 0x00000001;
35*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Unset VPLA_K_LD and VPLB_K_LD bit */
38*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL3);
39*4882a593Smuzhiyun tmp &= ~0x10000000;
40*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL3);
41*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL3);
42*4882a593Smuzhiyun tmp &= ~0x10000000;
43*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL3);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* Set VPLA_M and VPLB_M to 0x20 */
46*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL2);
47*4882a593Smuzhiyun tmp &= ~0x0000007f;
48*4882a593Smuzhiyun tmp |= 0x00000020;
49*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL2);
50*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL2);
51*4882a593Smuzhiyun tmp &= ~0x0000007f;
52*4882a593Smuzhiyun tmp |= 0x00000020;
53*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL2);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
56*4882a593Smuzhiyun clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
57*4882a593Smuzhiyun /* Set VPLA_K and VPLB_K for AXO: 25MHz */
58*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL3);
59*4882a593Smuzhiyun tmp &= ~0x000fffff;
60*4882a593Smuzhiyun tmp |= 0x00066666;
61*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL3);
62*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL3);
63*4882a593Smuzhiyun tmp &= ~0x000fffff;
64*4882a593Smuzhiyun tmp |= 0x00066666;
65*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL3);
66*4882a593Smuzhiyun } else {
67*4882a593Smuzhiyun /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
68*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL3);
69*4882a593Smuzhiyun tmp &= ~0x000fffff;
70*4882a593Smuzhiyun tmp |= 0x000f5800;
71*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL3);
72*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL3);
73*4882a593Smuzhiyun tmp &= ~0x000fffff;
74*4882a593Smuzhiyun tmp |= 0x000f5800;
75*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL3);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* wait 1 usec */
79*4882a593Smuzhiyun udelay(1);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
82*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL3);
83*4882a593Smuzhiyun tmp |= 0x10000000;
84*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL3);
85*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL3);
86*4882a593Smuzhiyun tmp |= 0x10000000;
87*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL3);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Unset VPLA_SNRST and VPLB_SNRST bit */
90*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL2);
91*4882a593Smuzhiyun tmp |= 0x10000000;
92*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL2);
93*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL2);
94*4882a593Smuzhiyun tmp |= 0x10000000;
95*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL2);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
98*4882a593Smuzhiyun tmp = readl(SC_VPLL27ACTRL);
99*4882a593Smuzhiyun tmp &= ~0x00000001;
100*4882a593Smuzhiyun writel(tmp, SC_VPLL27ACTRL);
101*4882a593Smuzhiyun tmp = readl(SC_VPLL27BCTRL);
102*4882a593Smuzhiyun tmp &= ~0x00000001;
103*4882a593Smuzhiyun writel(tmp, SC_VPLL27BCTRL);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
uniphier_pro4_pll_init(void)106*4882a593Smuzhiyun void uniphier_pro4_pll_init(void)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun vpll_init();
109*4882a593Smuzhiyun uniphier_ld4_dpll_ssc_en();
110*4882a593Smuzhiyun }
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