Home
last modified time | relevance | path

Searched +full:s +full:- +full:ahb (Results 1 – 25 of 904) sorted by relevance

12345678910>>...37

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Mukesh Savaliya <msavaliy@codeaurora.org>
11 - Akash Asthana <akashast@codeaurora.org>
24 - qcom,geni-se-qup
30 clock-names:
32 - const: m-ahb
33 - const: s-ahb
[all …]
/OK3568_Linux_fs/kernel/drivers/soc/versatile/
H A Dsoc-integrator.c1 // SPDX-License-Identifier: GPL-2.0-only
21 { .compatible = "arm,core-module-integrator", },
29 return "ASB little-endian"; in integrator_arch_str()
31 return "AHB little-endian"; in integrator_arch_str()
33 return "AHB-Lite system bus, bi-endian"; in integrator_arch_str()
35 return "AHB"; in integrator_arch_str()
37 return "AHB system bus, ASB processor bus"; in integrator_arch_str()
70 return sprintf(buf, "%s\n", integrator_arch_str(integrator_coreid)); in arch_show()
78 return sprintf(buf, "%s\n", integrator_fpga_str(integrator_coreid)); in fpga_show()
113 return -ENODEV; in integrator_soc_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/qcom/camss/
H A Dcamss.c1 // SPDX-License-Identifier: GPL-2.0
5 * Qualcomm MSM Camera Subsystem - Core
8 * Copyright (C) 2015-2018 Linaro Ltd.
11 #include <linux/media-bus-format.h>
22 #include <media/media-device.h>
23 #include <media/v4l2-async.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-mc.h>
26 #include <media/v4l2-fwnode.h>
37 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-imx35.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
34 unsigned char arm, ahb, sel; member
38 { .arm = 1, .ahb = 4, .sel = 0},
39 { .arm = 1, .ahb = 3, .sel = 1},
40 { .arm = 2, .ahb = 2, .sel = 0},
41 { .arm = 0, .ahb = 0, .sel = 0},
42 { .arm = 0, .ahb = 0, .sel = 0},
43 { .arm = 0, .ahb = 0, .sel = 0},
44 { .arm = 4, .ahb = 1, .sel = 0},
[all …]
H A Dclk-imx31.c1 // SPDX-License-Identifier: GPL-2.0-or-later
40 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
74 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); in _mx31_clocks_init()
75 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3); in _mx31_clocks_init()
76 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); in _mx31_clocks_init()
93 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14); in _mx31_clocks_init()
111 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18); in _mx31_clocks_init()
122 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8); in _mx31_clocks_init()
123 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); in _mx31_clocks_init()
141 for_each_compatible_node(osc_np, NULL, "fixed-clock") { in mx31_clocks_init_dt()
[all …]
H A Dclk-imx25.c1 // SPDX-License-Identifier: GPL-2.0-or-later
46 static const char *per_sel_clks[] = { "ahb", "upll", };
47 static const char *cko_sel_clks[] = { "dummy", "osc", "cpu", "ahb",
53 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
86 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
88 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in __mx25_clocks_init()
140 clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16); in __mx25_clocks_init()
142 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); in __mx25_clocks_init()
143 clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19); in __mx25_clocks_init()
144 clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20); in __mx25_clocks_init()
[all …]
H A Dclk-imx6q.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/clk-provider.h>
19 #include <dt-bindings/clock/imx6qdl-clock.h>
32 static const char *gpu_axi_sels[] = { "axi", "ahb", };
33 static const char *pre_axi_sels[] = { "axi", "ahb", };
50 static const char *pcie_axi_sels[] = { "axi", "ahb", };
57 static const char *vdo_axi_sels[] = { "axi", "ahb", };
65 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
149 return -ENOENT; in ldb_di_sel_by_clock_id()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie.txt3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sdm845" for sdm845
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/usb/
H A Dci-hdrc-usb2.txt4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
13 "fsl,imx7ulp-usb"
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/octeon-usb/
H A Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
31 * This Software, including technical data, may be subject to U.S. export
32 * control laws, including the U.S. Export Administration Act and its associated
102 * Core AHB Configuration Register (GAHBCFG)
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
106 * configuration parameters. The AHB is the processor interface to the O2P USB
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_matrix.h4 * SPDX-License-Identifier: GPL-2.0+
59 u32 reserve1[16 - AT91_MATRIX_MASTERS];
61 u32 reserve2[16 - AT91_MATRIX_SLAVES];
63 u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
67 u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */
101 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
103 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
152 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
154 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
223 /* USB Pad Pull-Up Control Register */
/OK3568_Linux_fs/u-boot/include/faraday/
H A Dftpci100.h8 * SPDX-License-Identifier: GPL-2.0+
14 /* AHB Control Registers */
16 unsigned int iosize; /* 0x00 - I/O Space Size Signal */
17 unsigned int prot; /* 0x04 - AHB Protection */
18 unsigned int rsved[8]; /* 0x08-0x24 - Reserved */
19 unsigned int conf; /* 0x28 - PCI Configuration */
20 unsigned int data; /* 0x2c - PCI Configuration DATA */
24 * FTPCI100_IOSIZE_REG's constant definitions
26 #define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */
37 * PCI_INT_MASK's bit definitions
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath10k/
H A Dahb.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2016-2017 Qualcomm Atheros, Inc. All rights reserved.
14 #include "ahb.h"
17 { .compatible = "qcom,ipq4019-wifi",
30 return &((struct ath10k_pci *)ar->drv_priv)->ahb[0]; in ath10k_ahb_priv()
37 iowrite32(value, ar_ahb->mem + offset); in ath10k_ahb_write32()
44 return ioread32(ar_ahb->mem + offset); in ath10k_ahb_read32()
51 return ioread32(ar_ahb->gcc_mem + offset); in ath10k_ahb_gcc_read32()
58 iowrite32(value, ar_ahb->tcsr_mem + offset); in ath10k_ahb_tcsr_write32()
65 return ioread32(ar_ahb->tcsr_mem + offset); in ath10k_ahb_tcsr_read32()
[all …]
/OK3568_Linux_fs/kernel/arch/mips/ath25/
H A Dar5312.c9 * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
65 pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", in ar5312_ahb_err_handler()
68 machine_restart("AHB error"); /* Catastrophic failure */ in ar5312_ahb_err_handler()
97 ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq)); in ar5312_misc_irq_unmask()
103 ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0); in ar5312_misc_irq_mask()
108 .name = "ar5312-misc",
153 if (request_irq(irq, ar5312_ahb_err_handler, 0, "ar5312-ahb-error", in ar5312_arch_init_irq()
155 pr_err("Failed to register ar5312-ahb-error interrupt\n"); in ar5312_arch_init_irq()
169 .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
174 .name = "physmap-flash",
[all …]
H A Dar2315_regs.h11 * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
81 #define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
82 #define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
92 /* AHB master arbitration control */
97 #define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
106 #define AR2315_CONFIG_AHB 0x00000001 /* EC-AHB bridge endian */
108 #define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
128 /* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0). */
163 #define AR2315_ISR_AHB 0x00000008 /* AHB error */
172 #define AR2315_GISR_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
[all …]
/OK3568_Linux_fs/kernel/drivers/pci/controller/
H A Dpci-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * pci-rcar-gen2: internal PCI bus support
26 /* AHB-PCI Bridge PCI communication registers */
108 struct rcar_pci_priv *priv = bus->sysdata; in rcar_pci_cfg_base()
114 /* Only one EHCI/OHCI device built-in */ in rcar_pci_cfg_base()
126 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG); in rcar_pci_cfg_base()
127 return priv->reg + (slot >> 1) * 0x100 + where; in rcar_pci_cfg_base()
136 struct device *dev = priv->dev; in rcar_pci_err_irq()
137 u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG); in rcar_pci_err_irq()
142 /* clear the error(s) */ in rcar_pci_err_irq()
[all …]
/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/net/
H A Dsnps,dwc-qos-ethernet.txt10 - compatible: One of:
11 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
12 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
13 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
15 - "snps,dwc-qos-ethernet-4.10"
17 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
19 - reg: Address and length of the register set for the device
20 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
21 same order. See ../clock/clock-bindings.txt.
22 - clock-names: May contain any/all of the following depending on the IP
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-ixp4xx/
H A Dcommon-pci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-ixp4xx/common-pci.c
11 * Copyright (C) 2003-2004 MontaVista Software, Inc.
26 #include <asm/dma-mapping.h>
87 pr_debug("%s failed\n", __func__); in check_master_abort()
105 * PCI workaround - only works if NP PCI space reads have in ixp4xx_pci_read_errata()
170 addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) | in ixp4xx_config_addr()
241 u8 bus_num = bus->number; in ixp4xx_pci_read_config()
264 u8 bus_num = bus->number; in ixp4xx_pci_write_config()
309 regs->ARM_pc += 4; in abort_handler()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu-sun4i-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
26 #include "ccu-sun4i-a10.h"
36 .hw.init = CLK_HW_INIT("pll-core",
48 * With sigma-delta modulation for fractional-N on the audio PLL,
71 .hw.init = CLK_HW_INIT("pll-audio-base",
89 .hw.init = CLK_HW_INIT("pll-video0",
104 .hw.init = CLK_HW_INIT("pll-ve",
117 .hw.init = CLK_HW_INIT("pll-ve",
130 .hw.init = CLK_HW_INIT("pll-ddr-base",
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
45 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
46 req->rate == 54000000) in sun4i_get_pll1_factors()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dsun6i-a31.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/reset/sun6i-a31-ccu.h>
52 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <1>;
61 #address-cells = <1>;
[all …]
H A Dimx35.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include "imx35-pinfunc.h"
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
38 #address-cells = <1>;
39 #size-cells = <0>;
42 compatible = "arm,arm1136jf-s";
48 avic: avic-interrupt-controller@68000000 {
49 compatible = "fsl,imx35-avic", "fsl,avic";
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A DKconfig115 default "fsl,ls1012a-pcie" if ARCH_LS1012A
116 default "fsl,ls1043a-pcie" if ARCH_LS1043A
117 default "fsl,ls1046a-pcie" if ARCH_LS1046A
118 default "fsl,ls2080a-pcie" if ARCH_LS2080A
154 stage instead of the RAM version of U-Boot. Once PPA is initialized,
155 the rest of U-Boot (including RAM version) runs at EL2.
157 prompt "FSL Layerscape PPA firmware loading-media select"
193 QSPI flash, this address is a directly memory-mapped.
208 QSPI flash, this address is a directly memory-mapped.
247 bool "Init the QSPI AHB bus"
[all …]
/OK3568_Linux_fs/kernel/drivers/usb/dwc2/
H A Dcore.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * core.c - DesignWare HS OTG Controller common routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
16 * 3. The names of the above-listed copyright holders may not be used
48 #include <linux/dma-mapping.h>
61 * dwc2_backup_global_registers() - Backup global controller registers.
71 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_backup_global_registers()
74 gr = &hsotg->gr_backup; in dwc2_backup_global_registers()
76 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL); in dwc2_backup_global_registers()
77 gr->gintmsk = dwc2_readl(hsotg, GINTMSK); in dwc2_backup_global_registers()
[all …]

12345678910>>...37