1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2010 Andes Technology Corporation 5*4882a593Smuzhiyun * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com> 6*4882a593Smuzhiyun * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __FTPCI100_H 12*4882a593Smuzhiyun #define __FTPCI100_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* AHB Control Registers */ 15*4882a593Smuzhiyun struct ftpci100_ahbc { 16*4882a593Smuzhiyun unsigned int iosize; /* 0x00 - I/O Space Size Signal */ 17*4882a593Smuzhiyun unsigned int prot; /* 0x04 - AHB Protection */ 18*4882a593Smuzhiyun unsigned int rsved[8]; /* 0x08-0x24 - Reserved */ 19*4882a593Smuzhiyun unsigned int conf; /* 0x28 - PCI Configuration */ 20*4882a593Smuzhiyun unsigned int data; /* 0x2c - PCI Configuration DATA */ 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * FTPCI100_IOSIZE_REG's constant definitions 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * PCI Configuration Register 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun #define PCI_INT_MASK 0x4c 32*4882a593Smuzhiyun #define PCI_MEM_BASE_SIZE1 0x50 33*4882a593Smuzhiyun #define PCI_MEM_BASE_SIZE2 0x54 34*4882a593Smuzhiyun #define PCI_MEM_BASE_SIZE3 0x58 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* 37*4882a593Smuzhiyun * PCI_INT_MASK's bit definitions 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun #define PCI_INTA_ENABLE (1 << 22) 40*4882a593Smuzhiyun #define PCI_INTB_ENABLE (1 << 23) 41*4882a593Smuzhiyun #define PCI_INTC_ENABLE (1 << 24) 42*4882a593Smuzhiyun #define PCI_INTD_ENABLE (1 << 25) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * PCI_MEM_BASE_SIZE1's constant definitions 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun #define FTPCI100_BASE_ADR_SIZE(x) ((ffs(x) - 1) << 16) /* 1M - 2048M */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define FTPCI100_MAX_FUNCTIONS 20 50*4882a593Smuzhiyun #define PCI_IRQ_LINES 4 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define MAX_BUS_NUM 256 53*4882a593Smuzhiyun #define MAX_DEV_NUM 32 54*4882a593Smuzhiyun #define MAX_FUN_NUM 8 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define PCI_MAX_BAR_PER_FUNC 6 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * PCI_MEM_SIZE 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun #define FTPCI100_MEM_SIZE(x) (ffs(x) << 24) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* This definition is used by pci_ftpci_init() */ 64*4882a593Smuzhiyun #define FTPCI100_BRIDGE_VENDORID 0x159b 65*4882a593Smuzhiyun #define FTPCI100_BRIDGE_DEVICEID 0x4321 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun void pci_ftpci_init(void); 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun struct pcibar { 70*4882a593Smuzhiyun unsigned int size; 71*4882a593Smuzhiyun unsigned int addr; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun struct pci_config { 75*4882a593Smuzhiyun unsigned int bus; 76*4882a593Smuzhiyun unsigned int dev; /* device */ 77*4882a593Smuzhiyun unsigned int func; 78*4882a593Smuzhiyun unsigned int pin; 79*4882a593Smuzhiyun unsigned short v_id; /* vendor id */ 80*4882a593Smuzhiyun unsigned short d_id; /* device id */ 81*4882a593Smuzhiyun struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1]; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #endif 85