1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * camss.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Qualcomm MSM Camera Subsystem - Core
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (c) 2015, The Linux Foundation. All rights reserved.
8*4882a593Smuzhiyun * Copyright (C) 2015-2018 Linaro Ltd.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/media-bus-format.h>
12*4882a593Smuzhiyun #include <linux/media.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/of.h>
16*4882a593Smuzhiyun #include <linux/of_graph.h>
17*4882a593Smuzhiyun #include <linux/pm_runtime.h>
18*4882a593Smuzhiyun #include <linux/pm_domain.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun #include <linux/videodev2.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <media/media-device.h>
23*4882a593Smuzhiyun #include <media/v4l2-async.h>
24*4882a593Smuzhiyun #include <media/v4l2-device.h>
25*4882a593Smuzhiyun #include <media/v4l2-mc.h>
26*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include "camss.h"
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define CAMSS_CLOCK_MARGIN_NUMERATOR 105
31*4882a593Smuzhiyun #define CAMSS_CLOCK_MARGIN_DENOMINATOR 100
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static const struct resources csiphy_res_8x16[] = {
34*4882a593Smuzhiyun /* CSIPHY0 */
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun .regulator = { NULL },
37*4882a593Smuzhiyun .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
38*4882a593Smuzhiyun .clock_rate = { { 0 },
39*4882a593Smuzhiyun { 0 },
40*4882a593Smuzhiyun { 0 },
41*4882a593Smuzhiyun { 100000000, 200000000 } },
42*4882a593Smuzhiyun .reg = { "csiphy0", "csiphy0_clk_mux" },
43*4882a593Smuzhiyun .interrupt = { "csiphy0" }
44*4882a593Smuzhiyun },
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* CSIPHY1 */
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun .regulator = { NULL },
49*4882a593Smuzhiyun .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
50*4882a593Smuzhiyun .clock_rate = { { 0 },
51*4882a593Smuzhiyun { 0 },
52*4882a593Smuzhiyun { 0 },
53*4882a593Smuzhiyun { 100000000, 200000000 } },
54*4882a593Smuzhiyun .reg = { "csiphy1", "csiphy1_clk_mux" },
55*4882a593Smuzhiyun .interrupt = { "csiphy1" }
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static const struct resources csid_res_8x16[] = {
60*4882a593Smuzhiyun /* CSID0 */
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun .regulator = { "vdda" },
63*4882a593Smuzhiyun .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
64*4882a593Smuzhiyun "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" },
65*4882a593Smuzhiyun .clock_rate = { { 0 },
66*4882a593Smuzhiyun { 0 },
67*4882a593Smuzhiyun { 0 },
68*4882a593Smuzhiyun { 0 },
69*4882a593Smuzhiyun { 100000000, 200000000 },
70*4882a593Smuzhiyun { 0 },
71*4882a593Smuzhiyun { 0 },
72*4882a593Smuzhiyun { 0 } },
73*4882a593Smuzhiyun .reg = { "csid0" },
74*4882a593Smuzhiyun .interrupt = { "csid0" }
75*4882a593Smuzhiyun },
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* CSID1 */
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun .regulator = { "vdda" },
80*4882a593Smuzhiyun .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
81*4882a593Smuzhiyun "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" },
82*4882a593Smuzhiyun .clock_rate = { { 0 },
83*4882a593Smuzhiyun { 0 },
84*4882a593Smuzhiyun { 0 },
85*4882a593Smuzhiyun { 0 },
86*4882a593Smuzhiyun { 100000000, 200000000 },
87*4882a593Smuzhiyun { 0 },
88*4882a593Smuzhiyun { 0 },
89*4882a593Smuzhiyun { 0 } },
90*4882a593Smuzhiyun .reg = { "csid1" },
91*4882a593Smuzhiyun .interrupt = { "csid1" }
92*4882a593Smuzhiyun },
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun static const struct resources_ispif ispif_res_8x16 = {
96*4882a593Smuzhiyun /* ISPIF */
97*4882a593Smuzhiyun .clock = { "top_ahb", "ahb", "ispif_ahb",
98*4882a593Smuzhiyun "csi0", "csi0_pix", "csi0_rdi",
99*4882a593Smuzhiyun "csi1", "csi1_pix", "csi1_rdi" },
100*4882a593Smuzhiyun .clock_for_reset = { "vfe0", "csi_vfe0" },
101*4882a593Smuzhiyun .reg = { "ispif", "csi_clk_mux" },
102*4882a593Smuzhiyun .interrupt = "ispif"
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun static const struct resources vfe_res_8x16[] = {
107*4882a593Smuzhiyun /* VFE0 */
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun .regulator = { NULL },
110*4882a593Smuzhiyun .clock = { "top_ahb", "vfe0", "csi_vfe0",
111*4882a593Smuzhiyun "vfe_ahb", "vfe_axi", "ahb" },
112*4882a593Smuzhiyun .clock_rate = { { 0 },
113*4882a593Smuzhiyun { 50000000, 80000000, 100000000, 160000000,
114*4882a593Smuzhiyun 177780000, 200000000, 266670000, 320000000,
115*4882a593Smuzhiyun 400000000, 465000000 },
116*4882a593Smuzhiyun { 0 },
117*4882a593Smuzhiyun { 0 },
118*4882a593Smuzhiyun { 0 },
119*4882a593Smuzhiyun { 0 },
120*4882a593Smuzhiyun { 0 },
121*4882a593Smuzhiyun { 0 },
122*4882a593Smuzhiyun { 0 } },
123*4882a593Smuzhiyun .reg = { "vfe0" },
124*4882a593Smuzhiyun .interrupt = { "vfe0" }
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun static const struct resources csiphy_res_8x96[] = {
129*4882a593Smuzhiyun /* CSIPHY0 */
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun .regulator = { NULL },
132*4882a593Smuzhiyun .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
133*4882a593Smuzhiyun .clock_rate = { { 0 },
134*4882a593Smuzhiyun { 0 },
135*4882a593Smuzhiyun { 0 },
136*4882a593Smuzhiyun { 100000000, 200000000, 266666667 } },
137*4882a593Smuzhiyun .reg = { "csiphy0", "csiphy0_clk_mux" },
138*4882a593Smuzhiyun .interrupt = { "csiphy0" }
139*4882a593Smuzhiyun },
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun /* CSIPHY1 */
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun .regulator = { NULL },
144*4882a593Smuzhiyun .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
145*4882a593Smuzhiyun .clock_rate = { { 0 },
146*4882a593Smuzhiyun { 0 },
147*4882a593Smuzhiyun { 0 },
148*4882a593Smuzhiyun { 100000000, 200000000, 266666667 } },
149*4882a593Smuzhiyun .reg = { "csiphy1", "csiphy1_clk_mux" },
150*4882a593Smuzhiyun .interrupt = { "csiphy1" }
151*4882a593Smuzhiyun },
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /* CSIPHY2 */
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun .regulator = { NULL },
156*4882a593Smuzhiyun .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer" },
157*4882a593Smuzhiyun .clock_rate = { { 0 },
158*4882a593Smuzhiyun { 0 },
159*4882a593Smuzhiyun { 0 },
160*4882a593Smuzhiyun { 100000000, 200000000, 266666667 } },
161*4882a593Smuzhiyun .reg = { "csiphy2", "csiphy2_clk_mux" },
162*4882a593Smuzhiyun .interrupt = { "csiphy2" }
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun static const struct resources csid_res_8x96[] = {
167*4882a593Smuzhiyun /* CSID0 */
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun .regulator = { "vdda" },
170*4882a593Smuzhiyun .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
171*4882a593Smuzhiyun "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" },
172*4882a593Smuzhiyun .clock_rate = { { 0 },
173*4882a593Smuzhiyun { 0 },
174*4882a593Smuzhiyun { 0 },
175*4882a593Smuzhiyun { 0 },
176*4882a593Smuzhiyun { 100000000, 200000000, 266666667 },
177*4882a593Smuzhiyun { 0 },
178*4882a593Smuzhiyun { 0 },
179*4882a593Smuzhiyun { 0 } },
180*4882a593Smuzhiyun .reg = { "csid0" },
181*4882a593Smuzhiyun .interrupt = { "csid0" }
182*4882a593Smuzhiyun },
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun /* CSID1 */
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun .regulator = { "vdda" },
187*4882a593Smuzhiyun .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
188*4882a593Smuzhiyun "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" },
189*4882a593Smuzhiyun .clock_rate = { { 0 },
190*4882a593Smuzhiyun { 0 },
191*4882a593Smuzhiyun { 0 },
192*4882a593Smuzhiyun { 0 },
193*4882a593Smuzhiyun { 100000000, 200000000, 266666667 },
194*4882a593Smuzhiyun { 0 },
195*4882a593Smuzhiyun { 0 },
196*4882a593Smuzhiyun { 0 } },
197*4882a593Smuzhiyun .reg = { "csid1" },
198*4882a593Smuzhiyun .interrupt = { "csid1" }
199*4882a593Smuzhiyun },
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun /* CSID2 */
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun .regulator = { "vdda" },
204*4882a593Smuzhiyun .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb",
205*4882a593Smuzhiyun "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" },
206*4882a593Smuzhiyun .clock_rate = { { 0 },
207*4882a593Smuzhiyun { 0 },
208*4882a593Smuzhiyun { 0 },
209*4882a593Smuzhiyun { 0 },
210*4882a593Smuzhiyun { 100000000, 200000000, 266666667 },
211*4882a593Smuzhiyun { 0 },
212*4882a593Smuzhiyun { 0 },
213*4882a593Smuzhiyun { 0 } },
214*4882a593Smuzhiyun .reg = { "csid2" },
215*4882a593Smuzhiyun .interrupt = { "csid2" }
216*4882a593Smuzhiyun },
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun /* CSID3 */
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun .regulator = { "vdda" },
221*4882a593Smuzhiyun .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb",
222*4882a593Smuzhiyun "csi3", "csi3_phy", "csi3_pix", "csi3_rdi" },
223*4882a593Smuzhiyun .clock_rate = { { 0 },
224*4882a593Smuzhiyun { 0 },
225*4882a593Smuzhiyun { 0 },
226*4882a593Smuzhiyun { 0 },
227*4882a593Smuzhiyun { 100000000, 200000000, 266666667 },
228*4882a593Smuzhiyun { 0 },
229*4882a593Smuzhiyun { 0 },
230*4882a593Smuzhiyun { 0 } },
231*4882a593Smuzhiyun .reg = { "csid3" },
232*4882a593Smuzhiyun .interrupt = { "csid3" }
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun static const struct resources_ispif ispif_res_8x96 = {
237*4882a593Smuzhiyun /* ISPIF */
238*4882a593Smuzhiyun .clock = { "top_ahb", "ahb", "ispif_ahb",
239*4882a593Smuzhiyun "csi0", "csi0_pix", "csi0_rdi",
240*4882a593Smuzhiyun "csi1", "csi1_pix", "csi1_rdi",
241*4882a593Smuzhiyun "csi2", "csi2_pix", "csi2_rdi",
242*4882a593Smuzhiyun "csi3", "csi3_pix", "csi3_rdi" },
243*4882a593Smuzhiyun .clock_for_reset = { "vfe0", "csi_vfe0", "vfe1", "csi_vfe1" },
244*4882a593Smuzhiyun .reg = { "ispif", "csi_clk_mux" },
245*4882a593Smuzhiyun .interrupt = "ispif"
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun static const struct resources vfe_res_8x96[] = {
249*4882a593Smuzhiyun /* VFE0 */
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun .regulator = { NULL },
252*4882a593Smuzhiyun .clock = { "top_ahb", "ahb", "vfe0", "csi_vfe0", "vfe_ahb",
253*4882a593Smuzhiyun "vfe0_ahb", "vfe_axi", "vfe0_stream"},
254*4882a593Smuzhiyun .clock_rate = { { 0 },
255*4882a593Smuzhiyun { 0 },
256*4882a593Smuzhiyun { 75000000, 100000000, 300000000,
257*4882a593Smuzhiyun 320000000, 480000000, 600000000 },
258*4882a593Smuzhiyun { 0 },
259*4882a593Smuzhiyun { 0 },
260*4882a593Smuzhiyun { 0 },
261*4882a593Smuzhiyun { 0 },
262*4882a593Smuzhiyun { 0 } },
263*4882a593Smuzhiyun .reg = { "vfe0" },
264*4882a593Smuzhiyun .interrupt = { "vfe0" }
265*4882a593Smuzhiyun },
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun /* VFE1 */
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun .regulator = { NULL },
270*4882a593Smuzhiyun .clock = { "top_ahb", "ahb", "vfe1", "csi_vfe1", "vfe_ahb",
271*4882a593Smuzhiyun "vfe1_ahb", "vfe_axi", "vfe1_stream"},
272*4882a593Smuzhiyun .clock_rate = { { 0 },
273*4882a593Smuzhiyun { 0 },
274*4882a593Smuzhiyun { 75000000, 100000000, 300000000,
275*4882a593Smuzhiyun 320000000, 480000000, 600000000 },
276*4882a593Smuzhiyun { 0 },
277*4882a593Smuzhiyun { 0 },
278*4882a593Smuzhiyun { 0 },
279*4882a593Smuzhiyun { 0 },
280*4882a593Smuzhiyun { 0 } },
281*4882a593Smuzhiyun .reg = { "vfe1" },
282*4882a593Smuzhiyun .interrupt = { "vfe1" }
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun };
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun /*
287*4882a593Smuzhiyun * camss_add_clock_margin - Add margin to clock frequency rate
288*4882a593Smuzhiyun * @rate: Clock frequency rate
289*4882a593Smuzhiyun *
290*4882a593Smuzhiyun * When making calculations with physical clock frequency values
291*4882a593Smuzhiyun * some safety margin must be added. Add it.
292*4882a593Smuzhiyun */
camss_add_clock_margin(u64 * rate)293*4882a593Smuzhiyun inline void camss_add_clock_margin(u64 *rate)
294*4882a593Smuzhiyun {
295*4882a593Smuzhiyun *rate *= CAMSS_CLOCK_MARGIN_NUMERATOR;
296*4882a593Smuzhiyun *rate = div_u64(*rate, CAMSS_CLOCK_MARGIN_DENOMINATOR);
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun /*
300*4882a593Smuzhiyun * camss_enable_clocks - Enable multiple clocks
301*4882a593Smuzhiyun * @nclocks: Number of clocks in clock array
302*4882a593Smuzhiyun * @clock: Clock array
303*4882a593Smuzhiyun * @dev: Device
304*4882a593Smuzhiyun *
305*4882a593Smuzhiyun * Return 0 on success or a negative error code otherwise
306*4882a593Smuzhiyun */
camss_enable_clocks(int nclocks,struct camss_clock * clock,struct device * dev)307*4882a593Smuzhiyun int camss_enable_clocks(int nclocks, struct camss_clock *clock,
308*4882a593Smuzhiyun struct device *dev)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun int ret;
311*4882a593Smuzhiyun int i;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun for (i = 0; i < nclocks; i++) {
314*4882a593Smuzhiyun ret = clk_prepare_enable(clock[i].clk);
315*4882a593Smuzhiyun if (ret) {
316*4882a593Smuzhiyun dev_err(dev, "clock enable failed: %d\n", ret);
317*4882a593Smuzhiyun goto error;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun return 0;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun error:
324*4882a593Smuzhiyun for (i--; i >= 0; i--)
325*4882a593Smuzhiyun clk_disable_unprepare(clock[i].clk);
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun return ret;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun /*
331*4882a593Smuzhiyun * camss_disable_clocks - Disable multiple clocks
332*4882a593Smuzhiyun * @nclocks: Number of clocks in clock array
333*4882a593Smuzhiyun * @clock: Clock array
334*4882a593Smuzhiyun */
camss_disable_clocks(int nclocks,struct camss_clock * clock)335*4882a593Smuzhiyun void camss_disable_clocks(int nclocks, struct camss_clock *clock)
336*4882a593Smuzhiyun {
337*4882a593Smuzhiyun int i;
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun for (i = nclocks - 1; i >= 0; i--)
340*4882a593Smuzhiyun clk_disable_unprepare(clock[i].clk);
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun /*
344*4882a593Smuzhiyun * camss_find_sensor - Find a linked media entity which represents a sensor
345*4882a593Smuzhiyun * @entity: Media entity to start searching from
346*4882a593Smuzhiyun *
347*4882a593Smuzhiyun * Return a pointer to sensor media entity or NULL if not found
348*4882a593Smuzhiyun */
camss_find_sensor(struct media_entity * entity)349*4882a593Smuzhiyun struct media_entity *camss_find_sensor(struct media_entity *entity)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun struct media_pad *pad;
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun while (1) {
354*4882a593Smuzhiyun pad = &entity->pads[0];
355*4882a593Smuzhiyun if (!(pad->flags & MEDIA_PAD_FL_SINK))
356*4882a593Smuzhiyun return NULL;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun pad = media_entity_remote_pad(pad);
359*4882a593Smuzhiyun if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
360*4882a593Smuzhiyun return NULL;
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun entity = pad->entity;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun if (entity->function == MEDIA_ENT_F_CAM_SENSOR)
365*4882a593Smuzhiyun return entity;
366*4882a593Smuzhiyun }
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun /*
370*4882a593Smuzhiyun * camss_get_pixel_clock - Get pixel clock rate from sensor
371*4882a593Smuzhiyun * @entity: Media entity in the current pipeline
372*4882a593Smuzhiyun * @pixel_clock: Received pixel clock value
373*4882a593Smuzhiyun *
374*4882a593Smuzhiyun * Return 0 on success or a negative error code otherwise
375*4882a593Smuzhiyun */
camss_get_pixel_clock(struct media_entity * entity,u32 * pixel_clock)376*4882a593Smuzhiyun int camss_get_pixel_clock(struct media_entity *entity, u32 *pixel_clock)
377*4882a593Smuzhiyun {
378*4882a593Smuzhiyun struct media_entity *sensor;
379*4882a593Smuzhiyun struct v4l2_subdev *subdev;
380*4882a593Smuzhiyun struct v4l2_ctrl *ctrl;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun sensor = camss_find_sensor(entity);
383*4882a593Smuzhiyun if (!sensor)
384*4882a593Smuzhiyun return -ENODEV;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun subdev = media_entity_to_v4l2_subdev(sensor);
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun ctrl = v4l2_ctrl_find(subdev->ctrl_handler, V4L2_CID_PIXEL_RATE);
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun if (!ctrl)
391*4882a593Smuzhiyun return -EINVAL;
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun *pixel_clock = v4l2_ctrl_g_ctrl_int64(ctrl);
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun return 0;
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun
camss_pm_domain_on(struct camss * camss,int id)398*4882a593Smuzhiyun int camss_pm_domain_on(struct camss *camss, int id)
399*4882a593Smuzhiyun {
400*4882a593Smuzhiyun if (camss->version == CAMSS_8x96) {
401*4882a593Smuzhiyun camss->genpd_link[id] = device_link_add(camss->dev,
402*4882a593Smuzhiyun camss->genpd[id], DL_FLAG_STATELESS |
403*4882a593Smuzhiyun DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun if (!camss->genpd_link[id])
406*4882a593Smuzhiyun return -EINVAL;
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun return 0;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
camss_pm_domain_off(struct camss * camss,int id)412*4882a593Smuzhiyun void camss_pm_domain_off(struct camss *camss, int id)
413*4882a593Smuzhiyun {
414*4882a593Smuzhiyun if (camss->version == CAMSS_8x96)
415*4882a593Smuzhiyun device_link_del(camss->genpd_link[id]);
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun /*
419*4882a593Smuzhiyun * camss_of_parse_endpoint_node - Parse port endpoint node
420*4882a593Smuzhiyun * @dev: Device
421*4882a593Smuzhiyun * @node: Device node to be parsed
422*4882a593Smuzhiyun * @csd: Parsed data from port endpoint node
423*4882a593Smuzhiyun *
424*4882a593Smuzhiyun * Return 0 on success or a negative error code on failure
425*4882a593Smuzhiyun */
camss_of_parse_endpoint_node(struct device * dev,struct device_node * node,struct camss_async_subdev * csd)426*4882a593Smuzhiyun static int camss_of_parse_endpoint_node(struct device *dev,
427*4882a593Smuzhiyun struct device_node *node,
428*4882a593Smuzhiyun struct camss_async_subdev *csd)
429*4882a593Smuzhiyun {
430*4882a593Smuzhiyun struct csiphy_lanes_cfg *lncfg = &csd->interface.csi2.lane_cfg;
431*4882a593Smuzhiyun struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2;
432*4882a593Smuzhiyun struct v4l2_fwnode_endpoint vep = { { 0 } };
433*4882a593Smuzhiyun unsigned int i;
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun v4l2_fwnode_endpoint_parse(of_fwnode_handle(node), &vep);
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun csd->interface.csiphy_id = vep.base.port;
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun mipi_csi2 = &vep.bus.mipi_csi2;
440*4882a593Smuzhiyun lncfg->clk.pos = mipi_csi2->clock_lane;
441*4882a593Smuzhiyun lncfg->clk.pol = mipi_csi2->lane_polarities[0];
442*4882a593Smuzhiyun lncfg->num_data = mipi_csi2->num_data_lanes;
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun lncfg->data = devm_kcalloc(dev,
445*4882a593Smuzhiyun lncfg->num_data, sizeof(*lncfg->data),
446*4882a593Smuzhiyun GFP_KERNEL);
447*4882a593Smuzhiyun if (!lncfg->data)
448*4882a593Smuzhiyun return -ENOMEM;
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun for (i = 0; i < lncfg->num_data; i++) {
451*4882a593Smuzhiyun lncfg->data[i].pos = mipi_csi2->data_lanes[i];
452*4882a593Smuzhiyun lncfg->data[i].pol = mipi_csi2->lane_polarities[i + 1];
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun return 0;
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun /*
459*4882a593Smuzhiyun * camss_of_parse_ports - Parse ports node
460*4882a593Smuzhiyun * @dev: Device
461*4882a593Smuzhiyun * @notifier: v4l2_device notifier data
462*4882a593Smuzhiyun *
463*4882a593Smuzhiyun * Return number of "port" nodes found in "ports" node
464*4882a593Smuzhiyun */
camss_of_parse_ports(struct camss * camss)465*4882a593Smuzhiyun static int camss_of_parse_ports(struct camss *camss)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun struct device *dev = camss->dev;
468*4882a593Smuzhiyun struct device_node *node = NULL;
469*4882a593Smuzhiyun struct device_node *remote = NULL;
470*4882a593Smuzhiyun int ret, num_subdevs = 0;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun for_each_endpoint_of_node(dev->of_node, node) {
473*4882a593Smuzhiyun struct camss_async_subdev *csd;
474*4882a593Smuzhiyun struct v4l2_async_subdev *asd;
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun if (!of_device_is_available(node))
477*4882a593Smuzhiyun continue;
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun remote = of_graph_get_remote_port_parent(node);
480*4882a593Smuzhiyun if (!remote) {
481*4882a593Smuzhiyun dev_err(dev, "Cannot get remote parent\n");
482*4882a593Smuzhiyun ret = -EINVAL;
483*4882a593Smuzhiyun goto err_cleanup;
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun asd = v4l2_async_notifier_add_fwnode_subdev(
487*4882a593Smuzhiyun &camss->notifier, of_fwnode_handle(remote),
488*4882a593Smuzhiyun sizeof(*csd));
489*4882a593Smuzhiyun of_node_put(remote);
490*4882a593Smuzhiyun if (IS_ERR(asd)) {
491*4882a593Smuzhiyun ret = PTR_ERR(asd);
492*4882a593Smuzhiyun goto err_cleanup;
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun csd = container_of(asd, struct camss_async_subdev, asd);
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun ret = camss_of_parse_endpoint_node(dev, node, csd);
498*4882a593Smuzhiyun if (ret < 0)
499*4882a593Smuzhiyun goto err_cleanup;
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun num_subdevs++;
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun return num_subdevs;
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun err_cleanup:
507*4882a593Smuzhiyun of_node_put(node);
508*4882a593Smuzhiyun return ret;
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun /*
512*4882a593Smuzhiyun * camss_init_subdevices - Initialize subdev structures and resources
513*4882a593Smuzhiyun * @camss: CAMSS device
514*4882a593Smuzhiyun *
515*4882a593Smuzhiyun * Return 0 on success or a negative error code on failure
516*4882a593Smuzhiyun */
camss_init_subdevices(struct camss * camss)517*4882a593Smuzhiyun static int camss_init_subdevices(struct camss *camss)
518*4882a593Smuzhiyun {
519*4882a593Smuzhiyun const struct resources *csiphy_res;
520*4882a593Smuzhiyun const struct resources *csid_res;
521*4882a593Smuzhiyun const struct resources_ispif *ispif_res;
522*4882a593Smuzhiyun const struct resources *vfe_res;
523*4882a593Smuzhiyun unsigned int i;
524*4882a593Smuzhiyun int ret;
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun if (camss->version == CAMSS_8x16) {
527*4882a593Smuzhiyun csiphy_res = csiphy_res_8x16;
528*4882a593Smuzhiyun csid_res = csid_res_8x16;
529*4882a593Smuzhiyun ispif_res = &ispif_res_8x16;
530*4882a593Smuzhiyun vfe_res = vfe_res_8x16;
531*4882a593Smuzhiyun } else if (camss->version == CAMSS_8x96) {
532*4882a593Smuzhiyun csiphy_res = csiphy_res_8x96;
533*4882a593Smuzhiyun csid_res = csid_res_8x96;
534*4882a593Smuzhiyun ispif_res = &ispif_res_8x96;
535*4882a593Smuzhiyun vfe_res = vfe_res_8x96;
536*4882a593Smuzhiyun } else {
537*4882a593Smuzhiyun return -EINVAL;
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun for (i = 0; i < camss->csiphy_num; i++) {
541*4882a593Smuzhiyun ret = msm_csiphy_subdev_init(camss, &camss->csiphy[i],
542*4882a593Smuzhiyun &csiphy_res[i], i);
543*4882a593Smuzhiyun if (ret < 0) {
544*4882a593Smuzhiyun dev_err(camss->dev,
545*4882a593Smuzhiyun "Failed to init csiphy%d sub-device: %d\n",
546*4882a593Smuzhiyun i, ret);
547*4882a593Smuzhiyun return ret;
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun for (i = 0; i < camss->csid_num; i++) {
552*4882a593Smuzhiyun ret = msm_csid_subdev_init(camss, &camss->csid[i],
553*4882a593Smuzhiyun &csid_res[i], i);
554*4882a593Smuzhiyun if (ret < 0) {
555*4882a593Smuzhiyun dev_err(camss->dev,
556*4882a593Smuzhiyun "Failed to init csid%d sub-device: %d\n",
557*4882a593Smuzhiyun i, ret);
558*4882a593Smuzhiyun return ret;
559*4882a593Smuzhiyun }
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun ret = msm_ispif_subdev_init(&camss->ispif, ispif_res);
563*4882a593Smuzhiyun if (ret < 0) {
564*4882a593Smuzhiyun dev_err(camss->dev, "Failed to init ispif sub-device: %d\n",
565*4882a593Smuzhiyun ret);
566*4882a593Smuzhiyun return ret;
567*4882a593Smuzhiyun }
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun for (i = 0; i < camss->vfe_num; i++) {
570*4882a593Smuzhiyun ret = msm_vfe_subdev_init(camss, &camss->vfe[i],
571*4882a593Smuzhiyun &vfe_res[i], i);
572*4882a593Smuzhiyun if (ret < 0) {
573*4882a593Smuzhiyun dev_err(camss->dev,
574*4882a593Smuzhiyun "Fail to init vfe%d sub-device: %d\n", i, ret);
575*4882a593Smuzhiyun return ret;
576*4882a593Smuzhiyun }
577*4882a593Smuzhiyun }
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun return 0;
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun /*
583*4882a593Smuzhiyun * camss_register_entities - Register subdev nodes and create links
584*4882a593Smuzhiyun * @camss: CAMSS device
585*4882a593Smuzhiyun *
586*4882a593Smuzhiyun * Return 0 on success or a negative error code on failure
587*4882a593Smuzhiyun */
camss_register_entities(struct camss * camss)588*4882a593Smuzhiyun static int camss_register_entities(struct camss *camss)
589*4882a593Smuzhiyun {
590*4882a593Smuzhiyun int i, j, k;
591*4882a593Smuzhiyun int ret;
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun for (i = 0; i < camss->csiphy_num; i++) {
594*4882a593Smuzhiyun ret = msm_csiphy_register_entity(&camss->csiphy[i],
595*4882a593Smuzhiyun &camss->v4l2_dev);
596*4882a593Smuzhiyun if (ret < 0) {
597*4882a593Smuzhiyun dev_err(camss->dev,
598*4882a593Smuzhiyun "Failed to register csiphy%d entity: %d\n",
599*4882a593Smuzhiyun i, ret);
600*4882a593Smuzhiyun goto err_reg_csiphy;
601*4882a593Smuzhiyun }
602*4882a593Smuzhiyun }
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun for (i = 0; i < camss->csid_num; i++) {
605*4882a593Smuzhiyun ret = msm_csid_register_entity(&camss->csid[i],
606*4882a593Smuzhiyun &camss->v4l2_dev);
607*4882a593Smuzhiyun if (ret < 0) {
608*4882a593Smuzhiyun dev_err(camss->dev,
609*4882a593Smuzhiyun "Failed to register csid%d entity: %d\n",
610*4882a593Smuzhiyun i, ret);
611*4882a593Smuzhiyun goto err_reg_csid;
612*4882a593Smuzhiyun }
613*4882a593Smuzhiyun }
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun ret = msm_ispif_register_entities(&camss->ispif, &camss->v4l2_dev);
616*4882a593Smuzhiyun if (ret < 0) {
617*4882a593Smuzhiyun dev_err(camss->dev, "Failed to register ispif entities: %d\n",
618*4882a593Smuzhiyun ret);
619*4882a593Smuzhiyun goto err_reg_ispif;
620*4882a593Smuzhiyun }
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun for (i = 0; i < camss->vfe_num; i++) {
623*4882a593Smuzhiyun ret = msm_vfe_register_entities(&camss->vfe[i],
624*4882a593Smuzhiyun &camss->v4l2_dev);
625*4882a593Smuzhiyun if (ret < 0) {
626*4882a593Smuzhiyun dev_err(camss->dev,
627*4882a593Smuzhiyun "Failed to register vfe%d entities: %d\n",
628*4882a593Smuzhiyun i, ret);
629*4882a593Smuzhiyun goto err_reg_vfe;
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun for (i = 0; i < camss->csiphy_num; i++) {
634*4882a593Smuzhiyun for (j = 0; j < camss->csid_num; j++) {
635*4882a593Smuzhiyun ret = media_create_pad_link(
636*4882a593Smuzhiyun &camss->csiphy[i].subdev.entity,
637*4882a593Smuzhiyun MSM_CSIPHY_PAD_SRC,
638*4882a593Smuzhiyun &camss->csid[j].subdev.entity,
639*4882a593Smuzhiyun MSM_CSID_PAD_SINK,
640*4882a593Smuzhiyun 0);
641*4882a593Smuzhiyun if (ret < 0) {
642*4882a593Smuzhiyun dev_err(camss->dev,
643*4882a593Smuzhiyun "Failed to link %s->%s entities: %d\n",
644*4882a593Smuzhiyun camss->csiphy[i].subdev.entity.name,
645*4882a593Smuzhiyun camss->csid[j].subdev.entity.name,
646*4882a593Smuzhiyun ret);
647*4882a593Smuzhiyun goto err_link;
648*4882a593Smuzhiyun }
649*4882a593Smuzhiyun }
650*4882a593Smuzhiyun }
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun for (i = 0; i < camss->csid_num; i++) {
653*4882a593Smuzhiyun for (j = 0; j < camss->ispif.line_num; j++) {
654*4882a593Smuzhiyun ret = media_create_pad_link(
655*4882a593Smuzhiyun &camss->csid[i].subdev.entity,
656*4882a593Smuzhiyun MSM_CSID_PAD_SRC,
657*4882a593Smuzhiyun &camss->ispif.line[j].subdev.entity,
658*4882a593Smuzhiyun MSM_ISPIF_PAD_SINK,
659*4882a593Smuzhiyun 0);
660*4882a593Smuzhiyun if (ret < 0) {
661*4882a593Smuzhiyun dev_err(camss->dev,
662*4882a593Smuzhiyun "Failed to link %s->%s entities: %d\n",
663*4882a593Smuzhiyun camss->csid[i].subdev.entity.name,
664*4882a593Smuzhiyun camss->ispif.line[j].subdev.entity.name,
665*4882a593Smuzhiyun ret);
666*4882a593Smuzhiyun goto err_link;
667*4882a593Smuzhiyun }
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun }
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun for (i = 0; i < camss->ispif.line_num; i++)
672*4882a593Smuzhiyun for (k = 0; k < camss->vfe_num; k++)
673*4882a593Smuzhiyun for (j = 0; j < ARRAY_SIZE(camss->vfe[k].line); j++) {
674*4882a593Smuzhiyun ret = media_create_pad_link(
675*4882a593Smuzhiyun &camss->ispif.line[i].subdev.entity,
676*4882a593Smuzhiyun MSM_ISPIF_PAD_SRC,
677*4882a593Smuzhiyun &camss->vfe[k].line[j].subdev.entity,
678*4882a593Smuzhiyun MSM_VFE_PAD_SINK,
679*4882a593Smuzhiyun 0);
680*4882a593Smuzhiyun if (ret < 0) {
681*4882a593Smuzhiyun dev_err(camss->dev,
682*4882a593Smuzhiyun "Failed to link %s->%s entities: %d\n",
683*4882a593Smuzhiyun camss->ispif.line[i].subdev.entity.name,
684*4882a593Smuzhiyun camss->vfe[k].line[j].subdev.entity.name,
685*4882a593Smuzhiyun ret);
686*4882a593Smuzhiyun goto err_link;
687*4882a593Smuzhiyun }
688*4882a593Smuzhiyun }
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun return 0;
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun err_link:
693*4882a593Smuzhiyun i = camss->vfe_num;
694*4882a593Smuzhiyun err_reg_vfe:
695*4882a593Smuzhiyun for (i--; i >= 0; i--)
696*4882a593Smuzhiyun msm_vfe_unregister_entities(&camss->vfe[i]);
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun msm_ispif_unregister_entities(&camss->ispif);
699*4882a593Smuzhiyun err_reg_ispif:
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun i = camss->csid_num;
702*4882a593Smuzhiyun err_reg_csid:
703*4882a593Smuzhiyun for (i--; i >= 0; i--)
704*4882a593Smuzhiyun msm_csid_unregister_entity(&camss->csid[i]);
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun i = camss->csiphy_num;
707*4882a593Smuzhiyun err_reg_csiphy:
708*4882a593Smuzhiyun for (i--; i >= 0; i--)
709*4882a593Smuzhiyun msm_csiphy_unregister_entity(&camss->csiphy[i]);
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun return ret;
712*4882a593Smuzhiyun }
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun /*
715*4882a593Smuzhiyun * camss_unregister_entities - Unregister subdev nodes
716*4882a593Smuzhiyun * @camss: CAMSS device
717*4882a593Smuzhiyun *
718*4882a593Smuzhiyun * Return 0 on success or a negative error code on failure
719*4882a593Smuzhiyun */
camss_unregister_entities(struct camss * camss)720*4882a593Smuzhiyun static void camss_unregister_entities(struct camss *camss)
721*4882a593Smuzhiyun {
722*4882a593Smuzhiyun unsigned int i;
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun for (i = 0; i < camss->csiphy_num; i++)
725*4882a593Smuzhiyun msm_csiphy_unregister_entity(&camss->csiphy[i]);
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun for (i = 0; i < camss->csid_num; i++)
728*4882a593Smuzhiyun msm_csid_unregister_entity(&camss->csid[i]);
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun msm_ispif_unregister_entities(&camss->ispif);
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun for (i = 0; i < camss->vfe_num; i++)
733*4882a593Smuzhiyun msm_vfe_unregister_entities(&camss->vfe[i]);
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun
camss_subdev_notifier_bound(struct v4l2_async_notifier * async,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)736*4882a593Smuzhiyun static int camss_subdev_notifier_bound(struct v4l2_async_notifier *async,
737*4882a593Smuzhiyun struct v4l2_subdev *subdev,
738*4882a593Smuzhiyun struct v4l2_async_subdev *asd)
739*4882a593Smuzhiyun {
740*4882a593Smuzhiyun struct camss *camss = container_of(async, struct camss, notifier);
741*4882a593Smuzhiyun struct camss_async_subdev *csd =
742*4882a593Smuzhiyun container_of(asd, struct camss_async_subdev, asd);
743*4882a593Smuzhiyun u8 id = csd->interface.csiphy_id;
744*4882a593Smuzhiyun struct csiphy_device *csiphy = &camss->csiphy[id];
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun csiphy->cfg.csi2 = &csd->interface.csi2;
747*4882a593Smuzhiyun subdev->host_priv = csiphy;
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun return 0;
750*4882a593Smuzhiyun }
751*4882a593Smuzhiyun
camss_subdev_notifier_complete(struct v4l2_async_notifier * async)752*4882a593Smuzhiyun static int camss_subdev_notifier_complete(struct v4l2_async_notifier *async)
753*4882a593Smuzhiyun {
754*4882a593Smuzhiyun struct camss *camss = container_of(async, struct camss, notifier);
755*4882a593Smuzhiyun struct v4l2_device *v4l2_dev = &camss->v4l2_dev;
756*4882a593Smuzhiyun struct v4l2_subdev *sd;
757*4882a593Smuzhiyun int ret;
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun list_for_each_entry(sd, &v4l2_dev->subdevs, list) {
760*4882a593Smuzhiyun if (sd->host_priv) {
761*4882a593Smuzhiyun struct media_entity *sensor = &sd->entity;
762*4882a593Smuzhiyun struct csiphy_device *csiphy =
763*4882a593Smuzhiyun (struct csiphy_device *) sd->host_priv;
764*4882a593Smuzhiyun struct media_entity *input = &csiphy->subdev.entity;
765*4882a593Smuzhiyun unsigned int i;
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun for (i = 0; i < sensor->num_pads; i++) {
768*4882a593Smuzhiyun if (sensor->pads[i].flags & MEDIA_PAD_FL_SOURCE)
769*4882a593Smuzhiyun break;
770*4882a593Smuzhiyun }
771*4882a593Smuzhiyun if (i == sensor->num_pads) {
772*4882a593Smuzhiyun dev_err(camss->dev,
773*4882a593Smuzhiyun "No source pad in external entity\n");
774*4882a593Smuzhiyun return -EINVAL;
775*4882a593Smuzhiyun }
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun ret = media_create_pad_link(sensor, i,
778*4882a593Smuzhiyun input, MSM_CSIPHY_PAD_SINK,
779*4882a593Smuzhiyun MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
780*4882a593Smuzhiyun if (ret < 0) {
781*4882a593Smuzhiyun dev_err(camss->dev,
782*4882a593Smuzhiyun "Failed to link %s->%s entities: %d\n",
783*4882a593Smuzhiyun sensor->name, input->name, ret);
784*4882a593Smuzhiyun return ret;
785*4882a593Smuzhiyun }
786*4882a593Smuzhiyun }
787*4882a593Smuzhiyun }
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun ret = v4l2_device_register_subdev_nodes(&camss->v4l2_dev);
790*4882a593Smuzhiyun if (ret < 0)
791*4882a593Smuzhiyun return ret;
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun return media_device_register(&camss->media_dev);
794*4882a593Smuzhiyun }
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun static const struct v4l2_async_notifier_operations camss_subdev_notifier_ops = {
797*4882a593Smuzhiyun .bound = camss_subdev_notifier_bound,
798*4882a593Smuzhiyun .complete = camss_subdev_notifier_complete,
799*4882a593Smuzhiyun };
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun static const struct media_device_ops camss_media_ops = {
802*4882a593Smuzhiyun .link_notify = v4l2_pipeline_link_notify,
803*4882a593Smuzhiyun };
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun /*
806*4882a593Smuzhiyun * camss_probe - Probe CAMSS platform device
807*4882a593Smuzhiyun * @pdev: Pointer to CAMSS platform device
808*4882a593Smuzhiyun *
809*4882a593Smuzhiyun * Return 0 on success or a negative error code on failure
810*4882a593Smuzhiyun */
camss_probe(struct platform_device * pdev)811*4882a593Smuzhiyun static int camss_probe(struct platform_device *pdev)
812*4882a593Smuzhiyun {
813*4882a593Smuzhiyun struct device *dev = &pdev->dev;
814*4882a593Smuzhiyun struct camss *camss;
815*4882a593Smuzhiyun int num_subdevs, ret;
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun camss = kzalloc(sizeof(*camss), GFP_KERNEL);
818*4882a593Smuzhiyun if (!camss)
819*4882a593Smuzhiyun return -ENOMEM;
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun atomic_set(&camss->ref_count, 0);
822*4882a593Smuzhiyun camss->dev = dev;
823*4882a593Smuzhiyun platform_set_drvdata(pdev, camss);
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun if (of_device_is_compatible(dev->of_node, "qcom,msm8916-camss")) {
826*4882a593Smuzhiyun camss->version = CAMSS_8x16;
827*4882a593Smuzhiyun camss->csiphy_num = 2;
828*4882a593Smuzhiyun camss->csid_num = 2;
829*4882a593Smuzhiyun camss->vfe_num = 1;
830*4882a593Smuzhiyun } else if (of_device_is_compatible(dev->of_node,
831*4882a593Smuzhiyun "qcom,msm8996-camss")) {
832*4882a593Smuzhiyun camss->version = CAMSS_8x96;
833*4882a593Smuzhiyun camss->csiphy_num = 3;
834*4882a593Smuzhiyun camss->csid_num = 4;
835*4882a593Smuzhiyun camss->vfe_num = 2;
836*4882a593Smuzhiyun } else {
837*4882a593Smuzhiyun ret = -EINVAL;
838*4882a593Smuzhiyun goto err_free;
839*4882a593Smuzhiyun }
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun camss->csiphy = devm_kcalloc(dev, camss->csiphy_num,
842*4882a593Smuzhiyun sizeof(*camss->csiphy), GFP_KERNEL);
843*4882a593Smuzhiyun if (!camss->csiphy) {
844*4882a593Smuzhiyun ret = -ENOMEM;
845*4882a593Smuzhiyun goto err_free;
846*4882a593Smuzhiyun }
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun camss->csid = devm_kcalloc(dev, camss->csid_num, sizeof(*camss->csid),
849*4882a593Smuzhiyun GFP_KERNEL);
850*4882a593Smuzhiyun if (!camss->csid) {
851*4882a593Smuzhiyun ret = -ENOMEM;
852*4882a593Smuzhiyun goto err_free;
853*4882a593Smuzhiyun }
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun camss->vfe = devm_kcalloc(dev, camss->vfe_num, sizeof(*camss->vfe),
856*4882a593Smuzhiyun GFP_KERNEL);
857*4882a593Smuzhiyun if (!camss->vfe) {
858*4882a593Smuzhiyun ret = -ENOMEM;
859*4882a593Smuzhiyun goto err_free;
860*4882a593Smuzhiyun }
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun v4l2_async_notifier_init(&camss->notifier);
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun num_subdevs = camss_of_parse_ports(camss);
865*4882a593Smuzhiyun if (num_subdevs < 0) {
866*4882a593Smuzhiyun ret = num_subdevs;
867*4882a593Smuzhiyun goto err_cleanup;
868*4882a593Smuzhiyun }
869*4882a593Smuzhiyun
870*4882a593Smuzhiyun ret = camss_init_subdevices(camss);
871*4882a593Smuzhiyun if (ret < 0)
872*4882a593Smuzhiyun goto err_cleanup;
873*4882a593Smuzhiyun
874*4882a593Smuzhiyun ret = dma_set_mask_and_coherent(dev, 0xffffffff);
875*4882a593Smuzhiyun if (ret)
876*4882a593Smuzhiyun goto err_cleanup;
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun camss->media_dev.dev = camss->dev;
879*4882a593Smuzhiyun strscpy(camss->media_dev.model, "Qualcomm Camera Subsystem",
880*4882a593Smuzhiyun sizeof(camss->media_dev.model));
881*4882a593Smuzhiyun camss->media_dev.ops = &camss_media_ops;
882*4882a593Smuzhiyun media_device_init(&camss->media_dev);
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun camss->v4l2_dev.mdev = &camss->media_dev;
885*4882a593Smuzhiyun ret = v4l2_device_register(camss->dev, &camss->v4l2_dev);
886*4882a593Smuzhiyun if (ret < 0) {
887*4882a593Smuzhiyun dev_err(dev, "Failed to register V4L2 device: %d\n", ret);
888*4882a593Smuzhiyun goto err_cleanup;
889*4882a593Smuzhiyun }
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun ret = camss_register_entities(camss);
892*4882a593Smuzhiyun if (ret < 0)
893*4882a593Smuzhiyun goto err_register_entities;
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun if (num_subdevs) {
896*4882a593Smuzhiyun camss->notifier.ops = &camss_subdev_notifier_ops;
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun ret = v4l2_async_notifier_register(&camss->v4l2_dev,
899*4882a593Smuzhiyun &camss->notifier);
900*4882a593Smuzhiyun if (ret) {
901*4882a593Smuzhiyun dev_err(dev,
902*4882a593Smuzhiyun "Failed to register async subdev nodes: %d\n",
903*4882a593Smuzhiyun ret);
904*4882a593Smuzhiyun goto err_register_subdevs;
905*4882a593Smuzhiyun }
906*4882a593Smuzhiyun } else {
907*4882a593Smuzhiyun ret = v4l2_device_register_subdev_nodes(&camss->v4l2_dev);
908*4882a593Smuzhiyun if (ret < 0) {
909*4882a593Smuzhiyun dev_err(dev, "Failed to register subdev nodes: %d\n",
910*4882a593Smuzhiyun ret);
911*4882a593Smuzhiyun goto err_register_subdevs;
912*4882a593Smuzhiyun }
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun ret = media_device_register(&camss->media_dev);
915*4882a593Smuzhiyun if (ret < 0) {
916*4882a593Smuzhiyun dev_err(dev, "Failed to register media device: %d\n",
917*4882a593Smuzhiyun ret);
918*4882a593Smuzhiyun goto err_register_subdevs;
919*4882a593Smuzhiyun }
920*4882a593Smuzhiyun }
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun if (camss->version == CAMSS_8x96) {
923*4882a593Smuzhiyun camss->genpd[PM_DOMAIN_VFE0] = dev_pm_domain_attach_by_id(
924*4882a593Smuzhiyun camss->dev, PM_DOMAIN_VFE0);
925*4882a593Smuzhiyun if (IS_ERR(camss->genpd[PM_DOMAIN_VFE0]))
926*4882a593Smuzhiyun return PTR_ERR(camss->genpd[PM_DOMAIN_VFE0]);
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun camss->genpd[PM_DOMAIN_VFE1] = dev_pm_domain_attach_by_id(
929*4882a593Smuzhiyun camss->dev, PM_DOMAIN_VFE1);
930*4882a593Smuzhiyun if (IS_ERR(camss->genpd[PM_DOMAIN_VFE1])) {
931*4882a593Smuzhiyun dev_pm_domain_detach(camss->genpd[PM_DOMAIN_VFE0],
932*4882a593Smuzhiyun true);
933*4882a593Smuzhiyun return PTR_ERR(camss->genpd[PM_DOMAIN_VFE1]);
934*4882a593Smuzhiyun }
935*4882a593Smuzhiyun }
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun pm_runtime_enable(dev);
938*4882a593Smuzhiyun
939*4882a593Smuzhiyun return 0;
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun err_register_subdevs:
942*4882a593Smuzhiyun camss_unregister_entities(camss);
943*4882a593Smuzhiyun err_register_entities:
944*4882a593Smuzhiyun v4l2_device_unregister(&camss->v4l2_dev);
945*4882a593Smuzhiyun err_cleanup:
946*4882a593Smuzhiyun v4l2_async_notifier_cleanup(&camss->notifier);
947*4882a593Smuzhiyun err_free:
948*4882a593Smuzhiyun kfree(camss);
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun return ret;
951*4882a593Smuzhiyun }
952*4882a593Smuzhiyun
camss_delete(struct camss * camss)953*4882a593Smuzhiyun void camss_delete(struct camss *camss)
954*4882a593Smuzhiyun {
955*4882a593Smuzhiyun v4l2_device_unregister(&camss->v4l2_dev);
956*4882a593Smuzhiyun media_device_unregister(&camss->media_dev);
957*4882a593Smuzhiyun media_device_cleanup(&camss->media_dev);
958*4882a593Smuzhiyun
959*4882a593Smuzhiyun pm_runtime_disable(camss->dev);
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun if (camss->version == CAMSS_8x96) {
962*4882a593Smuzhiyun dev_pm_domain_detach(camss->genpd[PM_DOMAIN_VFE0], true);
963*4882a593Smuzhiyun dev_pm_domain_detach(camss->genpd[PM_DOMAIN_VFE1], true);
964*4882a593Smuzhiyun }
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun kfree(camss);
967*4882a593Smuzhiyun }
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun /*
970*4882a593Smuzhiyun * camss_remove - Remove CAMSS platform device
971*4882a593Smuzhiyun * @pdev: Pointer to CAMSS platform device
972*4882a593Smuzhiyun *
973*4882a593Smuzhiyun * Always returns 0.
974*4882a593Smuzhiyun */
camss_remove(struct platform_device * pdev)975*4882a593Smuzhiyun static int camss_remove(struct platform_device *pdev)
976*4882a593Smuzhiyun {
977*4882a593Smuzhiyun struct camss *camss = platform_get_drvdata(pdev);
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun v4l2_async_notifier_unregister(&camss->notifier);
980*4882a593Smuzhiyun v4l2_async_notifier_cleanup(&camss->notifier);
981*4882a593Smuzhiyun camss_unregister_entities(camss);
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun if (atomic_read(&camss->ref_count) == 0)
984*4882a593Smuzhiyun camss_delete(camss);
985*4882a593Smuzhiyun
986*4882a593Smuzhiyun return 0;
987*4882a593Smuzhiyun }
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun static const struct of_device_id camss_dt_match[] = {
990*4882a593Smuzhiyun { .compatible = "qcom,msm8916-camss" },
991*4882a593Smuzhiyun { .compatible = "qcom,msm8996-camss" },
992*4882a593Smuzhiyun { }
993*4882a593Smuzhiyun };
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, camss_dt_match);
996*4882a593Smuzhiyun
camss_runtime_suspend(struct device * dev)997*4882a593Smuzhiyun static int __maybe_unused camss_runtime_suspend(struct device *dev)
998*4882a593Smuzhiyun {
999*4882a593Smuzhiyun return 0;
1000*4882a593Smuzhiyun }
1001*4882a593Smuzhiyun
camss_runtime_resume(struct device * dev)1002*4882a593Smuzhiyun static int __maybe_unused camss_runtime_resume(struct device *dev)
1003*4882a593Smuzhiyun {
1004*4882a593Smuzhiyun return 0;
1005*4882a593Smuzhiyun }
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun static const struct dev_pm_ops camss_pm_ops = {
1008*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1009*4882a593Smuzhiyun pm_runtime_force_resume)
1010*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(camss_runtime_suspend, camss_runtime_resume, NULL)
1011*4882a593Smuzhiyun };
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun static struct platform_driver qcom_camss_driver = {
1014*4882a593Smuzhiyun .probe = camss_probe,
1015*4882a593Smuzhiyun .remove = camss_remove,
1016*4882a593Smuzhiyun .driver = {
1017*4882a593Smuzhiyun .name = "qcom-camss",
1018*4882a593Smuzhiyun .of_match_table = camss_dt_match,
1019*4882a593Smuzhiyun .pm = &camss_pm_ops,
1020*4882a593Smuzhiyun },
1021*4882a593Smuzhiyun };
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun module_platform_driver(qcom_camss_driver);
1024*4882a593Smuzhiyun
1025*4882a593Smuzhiyun MODULE_ALIAS("platform:qcom-camss");
1026*4882a593Smuzhiyun MODULE_DESCRIPTION("Qualcomm Camera Subsystem driver");
1027*4882a593Smuzhiyun MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
1028*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1029