1*4882a593Smuzhiyun* USB2 ChipIdea USB controller for ci13xxx 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: should be one of: 5*4882a593Smuzhiyun "fsl,imx23-usb" 6*4882a593Smuzhiyun "fsl,imx27-usb" 7*4882a593Smuzhiyun "fsl,imx28-usb" 8*4882a593Smuzhiyun "fsl,imx6q-usb" 9*4882a593Smuzhiyun "fsl,imx6sl-usb" 10*4882a593Smuzhiyun "fsl,imx6sx-usb" 11*4882a593Smuzhiyun "fsl,imx6ul-usb" 12*4882a593Smuzhiyun "fsl,imx7d-usb" 13*4882a593Smuzhiyun "fsl,imx7ulp-usb" 14*4882a593Smuzhiyun "lsi,zevio-usb" 15*4882a593Smuzhiyun "qcom,ci-hdrc" 16*4882a593Smuzhiyun "chipidea,usb2" 17*4882a593Smuzhiyun "xlnx,zynq-usb-2.20a" 18*4882a593Smuzhiyun "nvidia,tegra20-udc" 19*4882a593Smuzhiyun "nvidia,tegra30-udc" 20*4882a593Smuzhiyun "nvidia,tegra114-udc" 21*4882a593Smuzhiyun "nvidia,tegra124-udc" 22*4882a593Smuzhiyun- reg: base address and length of the registers 23*4882a593Smuzhiyun- interrupts: interrupt for the USB controller 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunRecommended properies: 26*4882a593Smuzhiyun- phy_type: the type of the phy connected to the core. Should be one 27*4882a593Smuzhiyun of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this 28*4882a593Smuzhiyun property the PORTSC register won't be touched. 29*4882a593Smuzhiyun- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg" 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunDeprecated properties: 32*4882a593Smuzhiyun- usb-phy: phandle for the PHY device. Use "phys" instead. 33*4882a593Smuzhiyun- fsl,usbphy: phandle of usb phy that connects to the port. Use "phys" instead. 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunOptional properties: 36*4882a593Smuzhiyun- clocks: reference to the USB clock 37*4882a593Smuzhiyun- phys: reference to the USB PHY 38*4882a593Smuzhiyun- phy-names: should be "usb-phy" 39*4882a593Smuzhiyun- vbus-supply: reference to the VBUS regulator 40*4882a593Smuzhiyun- maximum-speed: limit the maximum connection speed to "full-speed". 41*4882a593Smuzhiyun- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts 42*4882a593Smuzhiyun- itc-setting: interrupt threshold control register control, the setting 43*4882a593Smuzhiyun should be aligned with ITC bits at register USBCMD. 44*4882a593Smuzhiyun- ahb-burst-config: it is vendor dependent, the required value should be 45*4882a593Smuzhiyun aligned with AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This 46*4882a593Smuzhiyun property is used to change AHB burst configuration, check the chipidea 47*4882a593Smuzhiyun spec for meaning of each value. If this property is not existed, it 48*4882a593Smuzhiyun will use the reset value. 49*4882a593Smuzhiyun- tx-burst-size-dword: it is vendor dependent, the tx burst size in dword 50*4882a593Smuzhiyun (4 bytes), This register represents the maximum length of a the burst 51*4882a593Smuzhiyun in 32-bit words while moving data from system memory to the USB 52*4882a593Smuzhiyun bus, the value of this property will only take effect if property 53*4882a593Smuzhiyun "ahb-burst-config" is set to 0, if this property is missing the reset 54*4882a593Smuzhiyun default of the hardware implementation will be used. 55*4882a593Smuzhiyun- rx-burst-size-dword: it is vendor dependent, the rx burst size in dword 56*4882a593Smuzhiyun (4 bytes), This register represents the maximum length of a the burst 57*4882a593Smuzhiyun in 32-bit words while moving data from the USB bus to system memory, 58*4882a593Smuzhiyun the value of this property will only take effect if property 59*4882a593Smuzhiyun "ahb-burst-config" is set to 0, if this property is missing the reset 60*4882a593Smuzhiyun default of the hardware implementation will be used. 61*4882a593Smuzhiyun- extcon: phandles to external connector devices. First phandle should point to 62*4882a593Smuzhiyun external connector, which provide "USB" cable events, the second should point 63*4882a593Smuzhiyun to external connector device, which provide "USB-HOST" cable events. If one 64*4882a593Smuzhiyun of the external connector devices is not required, empty <0> phandle should 65*4882a593Smuzhiyun be specified. 66*4882a593Smuzhiyun- phy-clkgate-delay-us: the delay time (us) between putting the PHY into 67*4882a593Smuzhiyun low power mode and gating the PHY clock. 68*4882a593Smuzhiyun- non-zero-ttctrl-ttha: after setting this property, the value of register 69*4882a593Smuzhiyun ttctrl.ttha will be 0x7f; if not, the value will be 0x0, this is the default 70*4882a593Smuzhiyun value. It needs to be very carefully for setting this property, it is 71*4882a593Smuzhiyun recommended that consult with your IC engineer before setting this value. 72*4882a593Smuzhiyun On the most of chipidea platforms, the "usage_tt" flag at RTL is 0, so this 73*4882a593Smuzhiyun property only affects siTD. 74*4882a593Smuzhiyun If this property is not set, the max packet size is 1023 bytes, and if 75*4882a593Smuzhiyun the total of packet size for pervious transactions are more than 256 bytes, 76*4882a593Smuzhiyun it can't accept any transactions within this frame. The use case is single 77*4882a593Smuzhiyun transaction, but higher frame rate. 78*4882a593Smuzhiyun If this property is set, the max packet size is 188 bytes, it can handle 79*4882a593Smuzhiyun more transactions than above case, it can accept transactions until it 80*4882a593Smuzhiyun considers the left room size within frame is less than 188 bytes, software 81*4882a593Smuzhiyun needs to make sure it does not send more than 90% 82*4882a593Smuzhiyun maximum_periodic_data_per_frame. The use case is multiple transactions, but 83*4882a593Smuzhiyun less frame rate. 84*4882a593Smuzhiyun- mux-controls: The mux control for toggling host/device output of this 85*4882a593Smuzhiyun controller. It's expected that a mux state of 0 indicates device mode and a 86*4882a593Smuzhiyun mux state of 1 indicates host mode. 87*4882a593Smuzhiyun- mux-control-names: Shall be "usb_switch" if mux-controls is specified. 88*4882a593Smuzhiyun- pinctrl-names: Names for optional pin modes in "default", "host", "device". 89*4882a593Smuzhiyun In case of HSIC-mode, "idle" and "active" pin modes are mandatory. In this 90*4882a593Smuzhiyun case, the "idle" state needs to pull down the data and strobe pin 91*4882a593Smuzhiyun and the "active" state needs to pull up the strobe pin. 92*4882a593Smuzhiyun- pinctrl-n: alternate pin modes 93*4882a593Smuzhiyun 94*4882a593Smuzhiyuni.mx specific properties 95*4882a593Smuzhiyun- fsl,usbmisc: phandler of non-core register device, with one 96*4882a593Smuzhiyun argument that indicate usb controller index 97*4882a593Smuzhiyun- disable-over-current: disable over current detect 98*4882a593Smuzhiyun- over-current-active-low: over current signal polarity is active low. 99*4882a593Smuzhiyun- over-current-active-high: over current signal polarity is active high. 100*4882a593Smuzhiyun It's recommended to specify the over current polarity. 101*4882a593Smuzhiyun- power-active-high: power signal polarity is active high 102*4882a593Smuzhiyun- external-vbus-divider: enables off-chip resistor divider for Vbus 103*4882a593Smuzhiyun- samsung,picophy-pre-emp-curr-control: HS Transmitter Pre-Emphasis Current 104*4882a593Smuzhiyun Control. This signal controls the amount of current sourced to the 105*4882a593Smuzhiyun USB_OTG*_DP and USB_OTG*_DN pins after a J-to-K or K-to-J transition. 106*4882a593Smuzhiyun The range is from 0x0 to 0x3, the default value is 0x1. 107*4882a593Smuzhiyun Details can refer to TXPREEMPAMPTUNE0 bits of USBNC_n_PHY_CFG1. 108*4882a593Smuzhiyun- samsung,picophy-dc-vol-level-adjust: HS DC Voltage Level Adjustment. 109*4882a593Smuzhiyun Adjust the high-speed transmitter DC level voltage. 110*4882a593Smuzhiyun The range is from 0x0 to 0xf, the default value is 0x3. 111*4882a593Smuzhiyun Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1. 112*4882a593Smuzhiyun 113*4882a593SmuzhiyunExample: 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun usb@f7ed0000 { 116*4882a593Smuzhiyun compatible = "chipidea,usb2"; 117*4882a593Smuzhiyun reg = <0xf7ed0000 0x10000>; 118*4882a593Smuzhiyun interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 119*4882a593Smuzhiyun clocks = <&chip CLKID_USB0>; 120*4882a593Smuzhiyun phys = <&usb_phy0>; 121*4882a593Smuzhiyun phy-names = "usb-phy"; 122*4882a593Smuzhiyun vbus-supply = <®_usb0_vbus>; 123*4882a593Smuzhiyun itc-setting = <0x4>; /* 4 micro-frames */ 124*4882a593Smuzhiyun /* Incremental burst of unspecified length */ 125*4882a593Smuzhiyun ahb-burst-config = <0x0>; 126*4882a593Smuzhiyun tx-burst-size-dword = <0x10>; /* 64 bytes */ 127*4882a593Smuzhiyun rx-burst-size-dword = <0x10>; 128*4882a593Smuzhiyun extcon = <0>, <&usb_id>; 129*4882a593Smuzhiyun phy-clkgate-delay-us = <400>; 130*4882a593Smuzhiyun mux-controls = <&usb_switch>; 131*4882a593Smuzhiyun mux-control-names = "usb_switch"; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593SmuzhiyunExample for HSIC: 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun usb@2184400 { 137*4882a593Smuzhiyun compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 138*4882a593Smuzhiyun reg = <0x02184400 0x200>; 139*4882a593Smuzhiyun interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; 140*4882a593Smuzhiyun clocks = <&clks IMX6QDL_CLK_USBOH3>; 141*4882a593Smuzhiyun fsl,usbphy = <&usbphynop1>; 142*4882a593Smuzhiyun fsl,usbmisc = <&usbmisc 2>; 143*4882a593Smuzhiyun phy_type = "hsic"; 144*4882a593Smuzhiyun dr_mode = "host"; 145*4882a593Smuzhiyun ahb-burst-config = <0x0>; 146*4882a593Smuzhiyun tx-burst-size-dword = <0x10>; 147*4882a593Smuzhiyun rx-burst-size-dword = <0x10>; 148*4882a593Smuzhiyun pinctrl-names = "idle", "active"; 149*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbh2_idle>; 150*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_usbh2_active>; 151*4882a593Smuzhiyun #address-cells = <1>; 152*4882a593Smuzhiyun #size-cells = <0>; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun usbnet: smsc@1 { 155*4882a593Smuzhiyun compatible = "usb424,9730"; 156*4882a593Smuzhiyun reg = <1>; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun }; 159